Blackfin Embedded Processor ADSP-BF538/ADSP-BF538F FEATURES PERIPHERALS Up to 533 MHz high performance Blackfin processor Parallel peripheral interface (PPI) supporting ITU-R 656 video data formats Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter 4 dual-channel, full-duplex synchronous serial ports, 2 supporting 16 stereo I S channels RISC-like register and instruction model for ease of programming and compiler friendly support 2 DMA controllers supporting 26 peripheral DMAs Advanced debug, trace, and performance monitoring 4 memory-to-memory DMAs Wide range of operating voltages (see Operating Conditions Controller area network (CAN) 2.0B controller on Page 23) 3 SPI-compatible ports Programmable on-chip voltage regulator Three 32-bit timer/counters with PWM support 316-ball Pb-free CSP BGA package 3 UARTs with support for IrDA 2 2 TWI controllers compatible with I C industry standard MEMORY Up to 54 general-purpose I/O pins (GPIO) Up to 148K bytes of on-chip memory (see Table 1 on Page 3) Real-time clock, watchdog timer, and 32-bit core timer Optional 8M bit parallel flash with boot option On-chip PLL capable of frequency multiplication Memory management unit providing memory protection Debug/JTAG interface External memory controller with glueless support for SDRAM, SRAM, flash, and ROM Flexible memory booting options from SPI and external memory JTAG VOLTAGE REGULATOR TEST AND EMULATION PERIPHERAL ACCESS BUS TWI0-1 INTERRUPT WATCHDOG CONTROLLER TIMER B CAN 2.0B GPIO PORT RTC C GPIO L1 L1 DMA DMA PPI INSTRUCTION DATA CONTROLLER1 CONTROLLER0 SPI1-2 MEMORY MEMORY GPIO GPIO TIMER0-2 PORT PORT D F UART1-2 DMA CORE DMA DMA SPI0 DMA BUS 1 EXTERNAL EXTERNAL CORE BUS 1 BUS 0 GPIO BUS 0 SPORT2-3 PORT UART0 E EXTERNAL PORT FLASH, SDRAMCONTROL SPORT0-1 16 8M BIT PARALLEL FLASH BOOT ROM (SEE TABLE 1) Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com DMA ACCESS BUS 1 DMA ACCESS BUS 0 PERIPHERAL ACCESS BUSADSP-BF538/ADSP-BF538F TABLE OF CONTENTS Features ................................................................. 1 Clock Signals ...................................................... 14 Memory ................................................................ 1 Booting Modes ................................................... 16 Peripherals ............................................................. 1 Instruction Set Description .................................... 16 General Description ................................................. 3 Development Tools .............................................. 16 Low Power Architecture ......................................... 3 Additional Information ........................................ 18 System Integration ................................................ 3 Related Signal Chains ........................................... 18 ADSP-BF538/ADSP-BF538F Processor Peripherals ....... 3 Pin Descriptions .................................................... 19 Blackfin Processor Core .......................................... 4 Specifications ........................................................ 23 Memory Architecture ............................................ 5 Operating Conditions ........................................... 23 DMA Controllers .................................................. 8 Electrical Characteristics ....................................... 25 Real-Time Clock ................................................... 9 Absolute Maximum Ratings ................................... 27 Watchdog Timer .................................................. 9 ESD Sensitivity ................................................... 27 Timers ............................................................... 9 Package Information ............................................ 27 Serial Ports (SPORTs) .......................................... 10 Timing Specifications ........................................... 28 Serial Peripheral Interface (SPI) Ports ...................... 10 Output Drive Currents ......................................... 47 2-Wire Interface ................................................. 10 Test Conditions .................................................. 49 UART Ports ...................................................... 11 Thermal Characteristics ........................................ 53 General-Purpose Ports ......................................... 11 316-Ball CSP BGA Ball Assignment ........................... 54 Parallel Peripheral Interface ................................... 11 Outline Dimensions ................................................ 57 Controller Area Network (CAN) Interface ................ 12 Surface-Mount Design .......................................... 57 Dynamic Power Management ................................ 13 Ordering Guide ..................................................... 58 Voltage Regulation .............................................. 14 REVISION HISTORY 11/13Rev. D to Rev. E Updated Development Tools .................................... 16 Added footnote 3 to Operating Conditions .................. 23 Updated Table 33 in Serial Port Timing ....................... 38 Added Timer Clock Timing ...................................... 44 Added missing timing specifications to Table 39 in Timer Cycle Timing ............................................... 45 Rev. E Page 2 of 60 November 2013