ADSP-BF544BBCZ-5A

Blackfin Embedded Processor ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 FEATURES PERIPHERALS Up to 600 MHz high performance Blackfin processor High speed USB On-the-Go (OTG) with integrated PHY Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs SD/SDIO controller RISC-like register and instruction model ATA/ATAPI-6 controller Wide range of operating voltages and flexible booting Up to 4 synchronous serial ports (SPORTs) options Up to 3 serial peripheral interfaces (SPI-compatible) Programmable on-chip voltage regulator Up to 4 UARTs, two with automatic H/W flow control 400-ball CSP BGA, RoHS compliant package Up to 2 CAN (controller area network) 2.0B interfaces Up to 2 TWI (2-wire interface) controllers MEMORY 8- or 16-bit asynchronous host DMA interface Up to 324K bytes of on-chip memory comprised of Multiple enhanced parallel peripheral interfaces (EPPIs), instruction SRAM/cache dedicated instruction SRAM data supporting ITU-R BT.656 video formats and 18-/24-bit LCD SRAM/cache dedicated data SRAM scratchpad SRAM connections External sync memory controller supporting either DDR Media transceiver (MXVR) for connection to a MOST network SDRAM or mobile DDR SDRAM Pixel compositor for overlays, alpha blending, and color External async memory controller supporting 8-/16-bit async conversion memories and burst flash devices Up to eleven 32-bit timers/counters with PWM support NAND flash controller Real-time clock (RTC) and watchdog timer 4 memory-to-memory DMA pairs, 2 with ext. requests Up/down counter with support for rotary encoder Memory management unit providing memory protection Up to 152 general-purpose I/O (GPIOs) Code security with Lockbox secure technology and 128-bit On-chip PLL capable of frequency multiplication AES/ARC4 data encryption Debug/JTAG interface One-time-programmable (OTP) memory VOLTAGE JTAG TEST AND WATCHDOG CAN (0-1) RTC OTP REGULATOR TIMER EMULATION TWI (0-1) HOST DMA PAB 16 TIMERS(0-10) INTERRUPTS B UART (0-1) COUNTER UART (2-3) L2 L1 L1 L1 SRAM INSTR ROM INSTR SRAM DATA SRAM KEYPAD SPI (0-1) SPI (2) 32-BIT DMA MXVR DAB1 32 DCB 32 EAB 64 DEB 32 SPORT (2-3) USB 16-BIT DMA SPORT (0-1) DAB0 16 EXTERNAL PORT BOOT SD / SDIO ROM NOR, DDR, MDDR ATAPI EPPI (0-2) DDR/MDDR ASYNC NAND FLASH 16 16 PIXEL CONTROLLER COMPOSITOR Figure 1. ADSP-BF549 Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2014 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com PORTS PORTSADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 TABLE OF CONTENTS Features ................................................................. 1 Voltage Regulation .............................................. 16 Memory ................................................................ 1 Clock Signals ...................................................... 17 Peripherals ............................................................. 1 Booting Modes ................................................... 18 General Description ................................................. 3 Instruction Set Description .................................... 21 Low Power Architecture ......................................... 4 Development Tools .............................................. 21 System Integration ................................................ 4 MXVR Board Layout Guidelines ............................. 22 Blackfin Processor Peripherals ................................. 4 Additional information ......................................... 23 Blackfin Processor Core .......................................... 4 Related Signal Chains ........................................... 23 Memory Architecture ............................................ 6 Lockbox Secure Technology Disclaimer .................... 23 DMA Controllers .................................................. 9 Pin Descriptions .................................................... 24 Real-Time Clock ................................................. 10 Specifications ........................................................ 34 Watchdog Timer ................................................ 10 Operating Conditions ........................................... 34 Timers ............................................................. 10 Electrical Characteristics ....................................... 36 Up/Down Counter and Thumbwheel Interface .......... 11 Absolute Maximum Ratings ................................... 40 Serial Ports (SPORTs) .......................................... 11 ESD Sensitivity ................................................... 41 Serial Peripheral Interface (SPI) Ports ...................... 11 Package Information ............................................ 41 UART Ports (UARTs) .......................................... 11 Timing Specifications ........................................... 42 Controller Area Network (CAN) ............................ 12 Output Drive Currents ......................................... 88 TWI Controller Interface ...................................... 12 Test Conditions .................................................. 90 Ports ................................................................ 12 Capacitive Loading .............................................. 90 Pixel Compositor (PIXC) ...................................... 13 Typical Rise and Fall Times ................................... 91 Enhanced Parallel Peripheral Interface (EPPI) ........... 13 Thermal Characteristics ........................................ 93 USB On-the-Go Dual-Role Device Controller ............ 13 400-Ball CSP BGA Package ...................................... 94 ATA/ATAPI-6 Interface ....................................... 14 Outline Dimensions .............................................. 100 Keypad Interface ................................................. 14 Surface-Mount Design ........................................ 100 Secure Digital (SD)/SDIO Controller ....................... 14 Automotive Products ............................................ 101 Code Security .................................................... 14 Ordering Guide ................................................... 101 Media Transceiver MAC Layer (MXVR) .................. 14 Dynamic Power Management ................................ 15 REVISION HISTORY 03/14Rev. D to Rev. E Added/changed package dimensions to Figure 88 in Outline Dimensions .............................................. 100 Updated Development Tools .................................... 21 Added low Alpha Package model to Ordering Guide ..... 101 Corrected SPI2 pin count in Port B configuration in Pin Multiplexing .................................................... 24 Corrected typographical error of parameter name in External DMA Request Timing ................................. 58 Added note to Table 42 in Serial PortsEnable and Three-State .......................... 63 Corrected t and t minimum specifications from t +1 to WL WH SCLK 1 t in Timer Cycle Timing ................................. 69 SCLK Rev. E Page 2 of 102 March 2014