Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 2 internal memory-to-memory DMAs and 1 internal memory FEATURES DMA controller Dual symmetric 600 MHz high performance Blackfin cores 12 general-purpose 32-bit timers/counters with PWM 328K bytes of on-chip memory capability (see Memory Architecture on Page 4) SPI-compatible port Each Blackfin core includes UART with support for IrDA Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, Dual watchdog timers 40-bit shifter Dual 32-bit core timers RISC-like register and instruction model for ease of pro 48 programmable flags (GPIO) gramming and compiler-friendly support On-chip phase-locked loop capable of 0.5 to 64 frequency Advanced debug, trace, and performance monitoring multiplication Wide range of operating voltages, (see Operating Conditions 2 parallel input/output peripheral interface units supporting on Page 20) ITU-R 656 video and glueless interface to analog front end 256-ball CSP BGA (2 sizes) and 297-ball PBGA ADCs package options 2 dual channel, full duplex synchronous serial ports support 2 PERIPHERALS ing eight stereo I S channels Dual 12-channel DMA controllers (supporting 24 peripheral DMAs) 2 memory-to-memory DMAs IRQ CONTROL/ JTAG TEST IRQ CONTROL/ VOLTA GE WATCHDOG EMULATION WATCHDOG REGULA TOR TIMER TIMER UART B B IrDA SPI L1 L1 L1 L1 L2 SRAM INSTRUCTION INSTRUCTION DATA DATA 128K BYTES MEMORY MEMORY MEMORY MEMORY SPORT0 IMDMA SPORT1 CORE SYSTEM/BUS INTERFACE CONTROLLER GPIO EAB DMA CONTROLLER1 32 TIMERS DMA CONTROLLER2 DEB DAB 16 BOOT ROM 16 32 PAB DAB EXTERNAL PORT PPI0 PPI1 FLASH/SDRAM CONTROL Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2009 Analog Devices, Inc. All rights reserved. ADSP-BF561 TABLE OF CONTENTS Features ................................................................. 1 Designing an Emulator-Compatible Processor Board ... 16 Peripherals ............................................................. 1 Related Documents .............................................. 16 Table of Contents ..................................................... 2 Pin Descriptions .................................................... 17 Revision History ...................................................... 2 Specifications ........................................................ 20 General Description ................................................. 3 Operating Conditions ........................................... 20 Portable Low Power Architecture ............................. 3 Electrical Characteristics ....................................... 21 Blackfin Processor Core .......................................... 3 Absolute Maximum Ratings ................................... 22 Memory Architecture ............................................ 4 Package Information ............................................ 22 DMA Controllers .................................................. 8 ESD Sensitivity ................................................... 22 Watchdog Timer .................................................. 8 Timing Specifications ........................................... 23 Timers ............................................................... 9 Output Drive Currents ......................................... 41 Serial Ports (SPORTs) ............................................ 9 Power Dissipation ............................................... 42 Serial Peripheral Interface (SPI) Port ......................... 9 Test Conditions .................................................. 42 UART Port .......................................................... 9 Environmental Conditions .................................... 44 Programmable Flags (PFx) .................................... 10 256-Ball CSP BGA (17 mm) Ball Assignment ............... 46 Parallel Peripheral Interface ................................... 10 256-Ball CSP BGA (12 mm) Ball Assignment ............... 51 Dynamic Power Management ................................ 11 297-Ball PBGA Ball Assignment ................................. 56 Voltage Regulation .............................................. 12 Outline Dimensions ................................................ 61 Clock Signals ..................................................... 13 Surface-Mount Design .......................................... 63 Booting Modes ................................................... 14 Automotive Products .............................................. 63 Instruction Set Description ................................... 14 Ordering Guide ..................................................... 63 Development Tools ............................................. 15 REVISION HISTORY 9/09Rev. D to Rev. E Correct all outstanding document errata. Revised Figure 5 .....................................................................13 Added 533 MHz operation Table 10 ..................................20 Removed reference to 1.8 V operation Table 12 ...............21 Added Table 17 and Figure 9 Power-Up Reset Timing ....23 Removed references to T from t parameter J SCLK Table 20 ...................................................................................26 Added new SPORT timing parameters and diagram Table 23 ...................................................................................32 Figure 21 .................................................................................33 Rev. E Page 2 of 64 September 2009