Blackfin+ Core Embedded Processor ADSP-BF700/701/702/703/704/705/706/707 FEATURES MEMORY Blackfin+ core with up to 400 MHz performance 136 kB L1 SRAM with multi-parity-bit protection (64 kB instruction, 64 kB data, 8 kB scratchpad) Dual 16-bit or single 32-bit MAC support per cycle Large on-chip L2 SRAM with ECC protection 16-bit complex MAC and many other instruction set enhancements 256 kB, 512 kB, 1 MB variants Instruction set compatible with previous Blackfin products On-chip L2 ROM (512 kB) Low-cost packaging L3 interface (CSP BGA only) optimized for lowest system power, providing 16-bit interface to DDR2 or LPDDR DRAM 88-Lead LFCSP VQ (QFN) package (12 mm 12 mm), devices (up to 200 MHz) RoHS compliant Security and one-time-programmable memory 184-Ball CSP BGA package (12 mm 12 mm 0.8 mm pitch), RoHS compliant Crypto hardware accelerators Low system power with < 100 mW core domain power at Fast secure boot for IP protection 400 MHz (< 0.25 mW/MHz) at 25C T JUNCTION memDMA encryption/decryption for fast run-time security PERIPHERALS FEATURES See Figure 1, Processor Block Diagram and Table 1, Processor Comparison SYSTEM CONTROL BLOCKS PERIPHERALS 1 TWI EMULATOR PLL & POWER FAULT EVENT WATCHDOG TEST & CONTROL MANAGEMENT MANAGEMENT CONTROL 8 TIMER 1 COUNTER 2 CAN L2 MEMORY UP TO 2 UART 1M BYTE SRAM 512K BYTE B ECC-PROTECTED ROM SPI HOST PORT (& DMA MEMORY 136K BYTE PARITY BIT PROTECTED 2x QUAD SPI PROTECTION) GPIO L1 SRAM INSTRUCTION/DATA 1x DUAL SPI 2 SPORT 1 MSI SYSTEM FABRIC (SD/SDIO) 1 PPI EXTERNAL ANALOG BUS HARDWARE SUB STATIC MEMORY INTERFACES FUNCTIONS SYSTEM CONTROLLER MEMORY OTP SYSTEM PROTECTION 2 CRC PROTECTION MEMORY 3 MDMA STREAMS HADC CRYPTO ENGINE (SECURITY) DYNAMIC MEMORY CONTROLLER 1 RTC LPDDR 1 USB 2.0 HS OTG 16 DDR2 Figure 1. Processor Block Diagram Blackfin, Blackfin+, and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2017 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.comADSP-BF700/701/702/703/704/705/706/707 TABLE OF CONTENTS Features . 1 GPIO Multiplexing for 12 mm 12 mm 88-Lead LFCSP (QFN) . 36 Peripherals Features . 1 ADSP-BF70x Designer Quick Reference 38 Memory 1 Specifications 50 Table Of Contents 2 Operating Conditions . 50 Revision History 2 Electrical Characteristics . 53 General Description . 3 HADC 58 Blackfin+ Processor Core 4 Package Information 59 Instruction Set Description . 5 Absolute Maximum Ratings . 59 Processor Infrastructure . 5 ESD Sensitivity . 59 Memory Architecture 7 Timing Specifications . 60 Security Features 8 Output Drive Currents . 102 Processor Safety Features 8 Test Conditions 104 Additional Processor Peripherals 9 Environmental Conditions 106 Power and Clock Management . 12 ADSP-BF70x 184-Ball CSP BGA Ball Assignments System Debug 15 (Numerical by Ball Number) 107 Development Tools . 15 ADSP-BF70x 12 mm 12 mm 88-Lead LFCSP (QFN) Additional Information 16 Lead Assignments (Numerical by Lead Number) 110 Related Signal Chains 16 Outline Dimensions 113 Security Features Disclaimer 17 Surface-Mount Design 114 ADSP-BF70x Detailed Signal Descriptions . 18 Automotive Products 115 184-Ball CSP BGA Signal Descriptions . 22 Ordering Guide . 116 GPIO Multiplexing for 184-Ball CSP BGA 29 12 mm 12 mm 88-Lead LFCSP (QFN) Signal Descriptions 31 REVISION HISTORY 7/2017Rev. A to Rev. B Change to Table 3, Clock Dividers . 14 Added Sentence to Description of DMC VREF in Table 6, ADSP-BF70x Detailed Signal Descriptions . 18 Added Sentence to V Parameter, Added V DDR VREF HADC0 VINx Parameter, Added Automotive Use Only Parameter Heading to Operating Conditions 50 Added Footnote 1 in Table 25, HADC DC Accuracy 58 Added Analog Input Voltage Parameter, Changes to Input Voltage Parameter, Change to Rating for DDR2/LPDDR Input Voltage Parameter, Changes to Footnotes in Table 28 in Absolute Maximum Ratings 59 Rev. B Page 2 of 116 July 2017