Mixed-Signal Control Processor with ARM Cortex-M4 ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data Two Serial Peripheral Interface (SPI-compatible) ports SYSTEM FEATURES Eight 32-bit general-purpose timers 100 MHz to 240 MHz ARM Cortex-M4 with floating-point unit Four Encoder Interfaces, 2 with frequency division 128K Byte to 384K Byte zero-wait-state L1 SRAM with Single power supply 16K Byte L1 cache 176-lead (24 mm 24 mm) RoHS compliant LQFP package Up to 2M Byte flash memory 120-lead (14 mm 14 mm) RoHS compliant LQFP package 16-bit asynchronous external memory interface Enhanced PWM units ANALOG SUBSYSTEM FEATURES Four 3rd/4th order SINC filters for glueless connection of iso- ADC controller (ADCC) and DAC controller (DACC) lated ADCs Two 16-bit SAR ADCs with up to 24 multiplexed inputs, Harmonic analysis engine supporting dual simultaneous conversion in 380 ns (16-bit, 10/100 Ethernet MAC no missing codes, 3.5LSB INL) Full Speed USB On-the-Go (OTG) Two 12-bit R-string DACs, with output rate up to 50 kHz Two CAN (controller area network) 2.0B interfaces Two 2.5 V precision voltage reference outputs Three UART ports (For details, see ADC/DAC Specifications on Page 36.) PERIPHERALS SYSTEM CONTROL BLOCKS 1 TWI CoreSight PLL & POWER FAULT EVENT SYSTEM TEST & CONTROL MANAGEMENT MANAGEMENT CONTROL WATCHDOGS 4 QUADRATURE ENCODER 12 PWM PAIRS 8 TIMER L1 CACHE L1 MEMORY 2 CAN UP TO 384K BYTE 16K BYTE PARITY-ENABLED L1 INSTRUCTION ZERO-WAIT-STATE SRAM 3 UART CACHE Cortex-M4 2 SPI 2x SPORT SYSTEM FABRIC 1 EMAC WITH IEEE 1588 (OPTIONAL) STATIC MEMORY ANALOG L3 MEMORY CONTROLLER SUBSYSTEM HARMONIC ANALYSIS ENGINE ASYNC INTERFACE (HAE) UP TO 2M BYTE ADCC DACC FLASH SINC FILTERS ADC DAC USB FS OTG (OPTIONAL) HARDWARE FUNCTIONS Figure 1. Block Diagram Rev. PrE Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. 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GPIO (40 OR 91)ADSP-CM402F/CM403F/CM407F/CM408F Preliminary Technical Data TABLE OF CONTENTS System Features ....................................................... 1 Related Documents .............................................. 15 Analog Subsystem Features ........................................ 1 Related Signal Chains ........................................... 16 General Description ................................................. 3 ADSP-CM402F/ADSP-CM403F Signal Descriptions ...... 17 Analog Subsystem ................................................. 4 ADSP-CM402F/ADSP-CM403F Multiplexed Pins ......... 22 ARM Cortex-M4 Core ........................................... 7 ADSP-CM407F/ADSP-CM408F Signal Descriptions ...... 24 EmbeddedICE ...................................................... 7 ADSP-CM407F/ADSP-CM408F Multiplexed Pins ......... 31 Processor Infrastructure ......................................... 7 Specifications ........................................................ 34 Memory Architecture ............................................ 8 Operating Conditions ........................................... 34 Security Features ................................................ 10 Electrical Characteristics ....................................... 35 Processor Reliability Features ................................. 10 ADC/DAC Specifications ...................................... 36 Additional Processor Peripherals ............................ 11 Flash Specifications .............................................. 43 General-Purpose Counters .................................... 12 Absolute Maximum Ratings ................................... 44 Serial Peripheral Interface (SPI) Ports ...................... 12 ESD Sensitivity ................................................... 44 UART Ports ...................................................... 12 Package Information ............................................ 44 TWI Controller Interface ...................................... 12 Timing Specifications ........................................... 45 Controller Area Network (CAN) ............................ 13 Output Drive Currents ......................................... 72 10/100 Ethernet MAC .......................................... 13 Environmental Conditions .................................... 73 USB 2.0 On-the-Go Dual-Role Device Controller ....... 13 120-Lead LQFP Lead Assignments ............................. 74 Clock and Power Management ............................... 14 176-Lead LQFP Lead Assignments ............................. 77 System Debug .................................................... 15 Outline Dimensions ................................................ 81 Development Tools ............................................. 15 Pre-Release Products ............................................... 82 REVISION HISTORY 09/13Revision PrD to Revision PrE Updated the Specifications section to include Flash information and timing data for all interfaces. See Specifications ....... 34 Rev. PrE Page 2 of 84 September 2013