SHARC+ Dual-Core
DSP with ARM Cortex-A5
ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573
SYSTEM FEATURES 17 mm 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP,
RoHS compliant
Dual-enhanced SHARC+ high performance floating-point
Low system power across automotive temperature range
cores
Up to 500 MHz per SHARC+ core MEMORY
Up to 3 Mb (384 kB) L1 SRAM memory per core with parity
Large on-chip L2 SRAM with ECC protection, up to 1 MB
(optional ability to configure as cache)
One L3 interface optimized for low system power, providing
32-bit, 40-bit, and 64-bit floating-point support
16-bit interface to DDR3 (supporting 1.5 V capable DDR3L
32-bit fixed point
devices), DDR2, or LPDDR1 SDRAM devices
Byte, short word, word, long word addressed
ADDITIONAL FEATURES
ARM Cortex-A5 core
Security and Protection
500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle
Cryptographic hardware accelerators
32 kB L1 instruction cache with parity/32 kB L1 data cache
Fast secure boot with IP protection
with parity
Support for ARM TrustZone
256 kB L2 cache with parity
Accelerators
Powerful DMA system
FIR, IIR offload engines
On-chip memory protection
Qualified for automotive applications
Integrated safety features
CORE 0 CORE 1 CORE 2
PERIPHERALS
SYSTEM CONTROL
SIGNAL ROUTING UNIT (SRU)
SECURITY AND PROTECTION
2 PRECISION CLOCK
SYSTEM PROTECTION (SPU) S S
GENERATORS
1x DAI
20
SYSTEM MEMORY ASRC FULL SPORT
1x PIN
PROTECTION UNIT (SMPU)
4 PAIRS 0-3
BUFFER
L1 CACHE (PARITY)
FAULT MANAGEMENT
1 S/PDIF Rx/Tx
32 kB L1 I-CACHE
L1 SRAM (PARITY) L1 SRAM (PARITY)
ARM TrustZone SECURITY
32 kB L1 D-CACHE
2
3 I C
3 Mb (384 kB) 3 Mb (384 kB)
DUAL CRC
L2 CACHE
6
SRAM/CACHE SRAM/CACHE
2 LINK PORTS
256 kB (PARITY)
WATCHDOGS
2 SPI + 1 QUAD SPI
OTP MEMORY
3 UARTs
THERMAL MONITOR UNIT (TMU)
1 EPPI
PROGRAM FLOW
SYSTEM CROSSBAR AND DMA SUBSYSTEM 8 TIMERS + 1 COUNTER
G
SYS EVENT CORE 0 (GIC)
P
ADC CONTROL MODULE
I
SYS EVENT CORES 1-2 (SEC)
(ACM)
9264
O
TRIGGER ROUTING (TRU) 2 CAN2.0
SD/SDIO/eMMC
L3 MEMORY SYSTEM SYSTEM
CLOCK, RESET, AND POWER
INTERFACE L2 MEMORY ACCELERATION
MLB 3-PIN
CLOCK GENERATION (CGU)
DSP FUNCTIONS
DDR3
1 EMAC
SRAM
CLOCK DISTRIBUTION
(FIR, IIR)
DDR2
(ECC)
UNIT (CDU)
LPDDR1 8x SHARC FLAGS
8 Mb (1 MB)
7
ENCRYPTION/DECRYPTION
RESET CONTROL (RCU)
1 USB 2.0 HS
POWER MANAGEMENT (DPM)
16 MLB 6-PIN
6
DATA
HADC (8 CHAN, 12-BIT)
DEBUG UNIT
84
TM
ARM CoreSight
WATCHPOINTS (SWU)
Figure 1. Processor Block Diagram
SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
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Specifications subject to change without notice. No license is granted by implication
Tel: 781.329.4700 2018 Analog Devices, Inc. All rights reserved.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners. Technical Support www.analog.comADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573
TABLE OF CONTENTS
System Features ....................................................... 1 ADSP-SC57x/ADSP-2157x Designer Quick Reference .... 45
Memory ................................................................ 1 Specifications ........................................................ 56
Additional Features .................................................. 1 Operating Conditions ........................................... 56
Table Of Contents .................................................... 2 Electrical Characteristics ....................................... 60
Revision History ...................................................... 2 HADC .............................................................. 64
General Description ................................................. 3 TMU ................................................................ 64
ARM Cortex-A5 Processor ...................................... 5 Absolute Maximum Ratings ................................... 65
SHARC Processor ................................................. 6 ESD Caution ...................................................... 65
SHARC+ Core Architecture .................................... 8 Timing Specifications ........................................... 66
System Infrastructure ........................................... 10 Output Drive Currents ....................................... 122
System Memory Map ........................................... 11 Test Conditions ................................................ 124
Security Features ................................................ 13 Environmental Conditions .................................. 126
Security Features Disclaimer .................................. 14 ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball
Assignments .................................................... 127
Safety Features ................................................... 14
Numerical by Ball Number .................................. 127
Processor Peripherals ........................................... 15
Alphabetical by Pin Name ................................... 130
System Acceleration ............................................ 19
Configuration of the 400-Ball CSP_BGA ................. 133
System Design .................................................... 20
ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead
System Debug .................................................... 22
Assignments .................................................... 134
Development Tools ............................................. 22
Numerical by Lead Number ................................. 134
Additional Information ........................................ 23
Alphabetical by Pin Name ................................... 136
Related Signal Chains .......................................... 23
Configuration of the 176-Lead LQFP Lead
ADSP-SC57x/ADSP-2157x Detailed Signal
Configuration ................................................ 137
Descriptions ...................................................... 24
Outline Dimensions .............................................. 138
400-Ball CSP_BGA Signal Descriptions ....................... 28
Surface-Mount Design ........................................ 139
GPIO Multiplexing for 400-Ball CSP_BGA Package ....... 35
Automotive Products ......................................... 140
176-Lead LQFP Signal Descriptions ........................... 38
Ordering Guide ................................................ 141
GPIO Multiplexing for 176-Lead LQFP Package ............ 43
REVISION HISTORY
6/2018Rev. A to Rev. B Changes to Program Trace Macrocell (PTM) Timing .... 120
Changes to System Features ........................................ 1 Changes to Test Conditions .................................... 124
Changes to Additional Features ................................... 1 Changes to Automotive Products ............................. 140
Changes to Table 2 and Table 3, General Description ....... 3 Changes to Ordering Guide .................................... 141
Changes to Operating Conditions .............................. 56
Deleted Package Information from Specifications .......... 56
Changes to Table 27 and Table 28, Clock Related Operating
Conditions ........................................................... 58
Changes to Electrical Characteristics ........................... 60
Changes to Table 29, Table 32, and Table 33, Total Internal
Power Dissipation .................................................. 62
Changes to Table 37, HADC Timing Specifications ........ 64
Rev. B | Page 2 of 142 | June 2018