SHARC+ Dual Core
DSP with ARM Cortex-A5
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
19 mm 19 mm 349/529 BGA (0.8 pitch), RoHS compliant
SYSTEM FEATURES
Low system power across automotive temperature range
Dual enhanced SHARC+ high performance floating-point
cores
MEMORY
Up to 500 MHz per SHARC+ core
Large on-chip L2 SRAM with ECC protection, up to 256 kB
Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core
On-chip L2 ROM (512 kB)
with parity (optional ability to configure as cache)
Two Level 3 (L3) interfaces optimized for low system power,
32-bit, 40-bit, and 64-bit floating-point support
providing a 16-bit interface to DDR3 (supporting 1.5 V
32-bit fixed point
capable DDR3L devices), DDR2, or LPDDR1 SDRAM devices
Byte, short-word, word, long-word addressed
ADDITIONAL FEATURES
ARM Cortex-A5 core
Security and Protection
500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle
Cryptographic hardware accelerators
32 kB L1 instruction cache/32 kB L1 data cache
Fast secure boot with IP protection
256 kB Level 2 (L2) cache with parity
Support for ARM TrustZone
Powerful DMA system
Accelerators
On-chip memory protection
High performance pipelined FFT/IFFT engine
Integrated safety features
FIR, IIR, HAE, SINC offload engines
PERIPHERALS
SYSTEM CONTROL
SIGNAL ROUTING UNIT (SRU)
SECURITY AND PROTECTION
22 PRECISION CLOCK
CORE 0 CORE 1 CORE 2
SYSTEM PROTECTION (SPU) GENERATORS
2x DAI
SYSTEM MEMORY ASRC FULL SPORT
2x PIN
24 PAIRS 24
PROTECTION UNIT (SMPU) BUFFER 4028
S S
FAULT MANAGEMENT
21 S/PDIF Rx/Tx
ARM TrustZone SECURITY
2
3 I C
DUAL CRC L1 CACHE
6
32 kB L1 I-CACHE 2 LINK PORTS
L1 SRAM (PARITY) L1 SRAM (PARITY)
WATCHDOGS
32 kB L1 D-CACHE
2 SPI + 1 QUAD SPI
5 Mb (640 kB) 5 Mb (640 kB)
OTP MEMORY
L2 CACHE
SRAM/CACHE SRAM/CACHE
3 UARTs
256 kB (PARITY)
THERMAL MONITOR UNIT (TMU)
1 EPPI
PROGRAM FLOW
3 ePWM
SYS EVENT CORE 0 (GIC)
8 TIMERS + 1 COUNTER
G
SYS EVENT CORES 1-2 (SEC)
ADC CONTROL MODULE
SYSTEM CROSSBAR AND DMA SUBSYSTEM P
(ACM)
TRIGGER ROUTING (TRU)
I
O
10280
ASYNC MEMORY (16-BIT)
CLOCK, RESET, AND POWER
2 CAN2.0
CLOCK GENERATION (CGU)
SD/SDIO/eMMC
L3 MEMORY SYSTEM SYSTEM
CLOCK DISTRIBUTION
UNIT (CDU)
MLB 3-PIN
INTERFACES L2 MEMORY ACCELERATION
SRAM DSP FUNCTIONS 2 EMAC
REAL TIME CLOCK (RTC) DDR3 DDR3
ROM ROM
DDR2 DDR2 (ECC) (FFT/IFFT, FIR, IIR, HAE/SINC)
2 Mb 2 Mb
SINC FILTER
RESET CONTROL (RCU)
2 Mb
LPDDR1 LPDDR1
(256 kB) (256 kB)
(256 kB)
ENCRYPTION/DECRYPTION
8x SHARC FLAGS
POWER MANAGEMENT (DPM) 10
2 USB 2.0 HS
16 16
6
DEBUG UNIT
MLB 6-PIN
DATA DATA
TM
ARM CoreSight
7
PCIe2.0 (1 lane)
WATCHPOINTS (SWU)
HADC (8 CHAN, 12-BIT)
8
Figure 1. Processor Block Diagram
SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. A Document Feedback
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Specifications subject to change without notice. No license is granted by implication
Tel: 781.329.4700 2017 Analog Devices, Inc. All rights reserved.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners. Technical Support www.analog.comADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
TABLE OF CONTENTS
System Features ....................................................... 1 ADSP-SC58x/ADSP-2158x Designer Quick Reference .... 58
Memory ................................................................ 1 Specifications ........................................................ 80
Additional Features .................................................. 1 Operating Conditions ........................................... 80
Table Of Contents .................................................... 2 Electrical Characteristics ....................................... 84
Revision History ...................................................... 3 HADC .............................................................. 88
General Description ................................................. 4 TMU ................................................................ 88
ARM Cortex-A5 Processor ...................................... 6 Absolute Maximum Ratings ................................... 89
SHARC Processor ................................................. 7 ESD Caution ...................................................... 89
SHARC+ Core Architecture .................................... 9 Package Information ............................................ 89
System Infrastructure ........................................... 11 Timing Specifications ........................................... 90
System Memory Map ........................................... 12 Output Drive Currents ....................................... 154
Security Features ................................................ 15 Test Conditions ................................................ 156
Safety Features ................................................... 15 Environmental Conditions .................................. 158
Processor Peripherals ........................................... 16 ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball
Assignments .................................................... 159
System Acceleration ............................................ 21
Numerical by Ball Number .................................. 159
System Design .................................................... 21
Alphabetical by Pin Name ................................... 161
System Debug .................................................... 24
Configuration of the 349-Ball CSP_BGA ................. 163
Development Tools ............................................. 24
ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball
Additional Information ........................................ 25
Assignments .................................................... 164
Related Signal Chains .......................................... 25
Numerical by Ball Number .................................. 164
Security Features Disclaimer .................................. 25
Alphabetical by Pin Name ................................... 167
ADSP-SC58x/ADSP-2158x Detailed Signal
Configuration of the 529-Ball CSP_BGA ................. 170
Descriptions ...................................................... 26
Outline Dimensions .............................................. 171
349-Ball CSP_BGA Signal Descriptions ....................... 31
Surface-Mount Design ........................................ 172
GPIO Multiplexing for the 349-Ball CSP_BGA Package .. 40
Planned Automotive Production Products .............. 173
529-Ball CSP_BGA Signal Descriptions ....................... 43
Ordering Guide ................................................ 174
GPIO Multiplexing for the 529-Ball CSP_BGA Package .. 55
Rev. A | Page 2 of 174 | July 2017