TigerSHARC Embedded Processor ADSP-TS101S FEATURES BENEFITS 300 MHz, 3.3 ns instruction cycle rate Provides high performance Static Superscalar DSP opera- tions, optimized for telecommunications infrastructure 6M bits of internalon-chipSRAM memory and other large, demanding multiprocessor DSP 19 mm 19 mm (484-ball) CSP-BGA or 27 mm 27 mm applications (625-ball) PBGA package Performs exceptionally well on DSP algorithm and I/O bench- Dual computation blockseach containing an ALU, a multi- marks (see benchmarks in Table 1 and Table 2) plier, a shifter, and a register file Supports low overhead DMA transfers between internal Dual integer ALUs, providing data addressing and pointer memory, external memory, memory-mapped peripherals, manipulation link ports, other DSPs (multiprocessor), and host Integrated I/O includes 14-channel DMA controller, external processors port, 4 link ports, SDRAM controller, programmable flag Eases DSP programming through extremely flexible instruc- pins, 2 timers, and timer expired pin for system integration tion set and high-level language-friendly DSP architecture 1149.1 IEEE compliant JTAG test access port for on-chip Enables scalable multiprocessing systems with low commu- emulation nications overhead On-chip arbitration for glueless multiprocessing with up to 8 TigerSHARC processors on a bus COMPUTATIONAL BLOCKS PROGRAMSEQUENCER DATAADDRESS GENERATION INTERNALMEMORY 6 JTAG PORT MEMORY MEMORY MEMORY PC BTB IRQ 32 32 SHIFTER INTEGER INTEGER M0 M1 M2 JALU KALU 64K 32 64K 32 64K32 ADDR IAB 32 32 32 32 SDRAM CONTROLLER FETCH AD AD AD ALU MULTIPLIER EXTERNAL PORT 32 M0 ADDR X MULTIPROCESSOR M0DATA 128 REGISTER INTERFACE FILE 32 3232 HOSTINTERFACE 32 ADDR M1 ADDR 128 128 INPUTFIFO 64 M1DATA 128 DAB DATA OUTPUTBUFFER 32 DAB M2 ADDR OUTPUTFIFO 128 M2DATA CNTRL 128 128 CLUSTERBUS I/OADDRESS 32 ARBITER Y REGISTER I/O PROCESSOR 3 FILE L0 3232 8 DMA LINKPORT 3 CONTROLLER CONTROLLER MULTIPLIER L1 8 DMAADDRESS LINK 32 256 256 3 LINKDATA PORTS DMADATA ALU L2 8 CONTROL/ CONTROL/ STATUS/ STATUS/ 3 SHIFTER TCBs BUFFERS L3 8 Figure 1. Functional Block Diagram TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781/329-4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781/326-8703 2021 Analog Devices, Inc. All rights reserved.ADSP-TS101S TABLE OF CONTENTS Features ................................................................. 1 Designing an Emulator-Compatible DSP Board (Target) .......................................... 11 Benefits ................................................................. 1 Additional Information ........................................ 11 Table of Contents ..................................................... 2 Pin Function Descriptions ........................................ 12 Revision History ...................................................... 2 Pin States at Reset ................................................ 12 General Description ................................................. 3 Pin Definitions ................................................... 12 Dual Compute Blocks ............................................ 4 Strap Pin Function Descriptions ................................ 19 Data Alignment Buffer (DAB) .................................. 4 Specifications ........................................................ 20 Dual Integer ALUs (IALUs) .................................... 4 Operating Conditions ........................................... 20 Program Sequencer ............................................... 5 Electrical Characteristics ....................................... 20 On-Chip SRAM Memory ........................................ 5 Absolute Maximum Ratings ................................... 21 External Port (Off-Chip Memory/Peripherals Interface) ................ 6 ESD Caution ...................................................... 21 DMA Controller ................................................... 7 Timing Specifications ........................................... 21 Link Ports ........................................................... 9 Output Drive Currents ......................................... 32 Timer and General-Purpose I/O ............................... 9 Test Conditions .................................................. 34 Reset and Booting ................................................. 9 Environmental Conditions .................................... 36 Low Power Operation ............................................ 9 PBGA Pin Configurations ........................................ 37 Clock Domains .................................................... 9 Outline Dimensions ................................................ 43 Output Pin Drive Strength Control ......................... 10 Surface-Mount Design ............................................. 44 Power Supplies ................................................... 10 Ordering Guide ..................................................... 45 Filtering Reference Voltage and Clocks .................... 10 Development Tools ............................................. 10 REVISION HISTORY 4/21Rev. C to Rev. D Changes to Operating Conditions .............................. 20 Changes to Electrical Characteristics ........................... 20 Removed Package Information section Changes to package diagram per PCN 20 0165 484-Ball Chip Scale Package Ball Grid Array CSP BGA (B-484-1) Dimen- sions shown in millimeters ....................................... 43 Changes to package diagram per PCN 20 0165 625-Ball Plas- tic Ball Grid Array PBGA (B-625-2) Dimensions shown in millimeters ........................................................... 44 Changes to Ordering Guide ...................................... 45 Rev. D Page 2 of 45 April 2021