TigerSHARC Embedded Processor a ADSP-TS201S KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate Provides high performance static superscalar DSP operations, optimized for telecommunications 24M bits of internalon-chipDRAM memory infrastructure and other large, demanding multiprocessor 25 mm 25 mm (576-ball) thermally enhanced ball grid DSP applications array package Performs exceptionally well on DSP algorithm and I/O Dual-computation blockseach containing an ALU, a benchmarks (see benchmarks in Table 1) multiplier, a shifter, a register file, and a communications Supports low overhead DMA transfers between internal logic unit (CLU) memory, external memory, memory-mapped peripherals, Dual-integer ALUs, providing data addressing and pointer link ports, host processors, and other manipulation (multiprocessor) DSPs Integrated I/O includes 14-channel DMA controller, external Eases DSP programming through extremely flexible instruc- port, four link ports, SDRAM controller, programmable tion set and high-level-language-friendly DSP architecture flag pins, two timers, and timer expired pin for system Enables scalable multiprocessing systems with low commu- integration nications overhead 1149.1 IEEE-compliant JTAG test access port for on-chip Provides on-chip arbitration for glueless multiprocessing emulation Single-precision IEEE 32-bit and extended-precision 40-bit floating-point data formats and 8-, 16-, 32-, and 64-bit fixed-point data formats JTAGPORT DATAADDRESS GENERATION 24MBITSINTERNAL MEMORY SOCBUS 6 32 32 MEMORYBLOCKS INTEGER INTEGER JTAG JALU KALU (PAGECACHE) EXTERNAL 32-BIT 32-BIT 32-BIT 32-BIT 4CROSSBARCONNECT PORT PROGRAM SEQUENCER 32 A A A A D D D D ADDR 32 HOST J-BUSADDR ADDR FETCH 64 MULTI- DATA 128 J-BUSDATA PROC 8 SDRAM CTRL 32 K-BUSADDR CTRL 10 BTB C-BUS CTRL 128 K-BUSDATA ARB SOC I-BUSADDR 32 EXTDMA I/F REQ 4 I-BUSDATA 128 DMA PC LINKPORTS S-BUSADDR 21 4 8 IN L0 4 128 S-BUSDATA OUT 8 IAB T 4 8 IN L1 4 OUT 8 4 IN 8 L2 4 128 128 OUT 8 4 X Y 8 IN REGISTER REGISTER 128 128 SHIFT ALU MUL MUL ALU SHIFT L3 4 CLU CLU FILE DAB DAB FILE OUT 8 32-BIT32-BIT 32-BIT 32-BIT COMPUTATIONAL BLOCKS Figure 1. Functional Block Diagram TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2006 Analog Devices, Inc. All rights reserved. OBSOLETEADSP-TS201S TABLE OF CONTENTS General Description ................................................. 3 Test Conditions .................................................. 37 Dual Compute Blocks ............................................ 4 Output Disable Time ......................................... 37 Data Alignment Buffer (DAB) .................................. 4 Output Enable Time ......................................... 38 Dual Integer ALU (IALU) ....................................... 4 Capacitive Loading ........................................... 38 Program Sequencer ............................................... 5 Environmental Conditions .................................... 40 Interrupt Controller ........................................... 5 Thermal Characteristics ..................................... 40 Flexible Instruction Set ........................................ 5 576-Ball BGA ED Pin Configurations ......................... 41 DSP Memory ....................................................... 5 Outline Dimensions ................................................ 45 External Port (Off-Chip Memory/Peripherals Surface Mount Design .......................................... 45 Interface) ......................................................... 6 Ordering Guide ..................................................... 46 Host Interface ................................................... 7 Multiprocessor Interface ...................................... 7 REVISION HISTORY SDRAM Controller ............................................ 7 12/06Rev. B to Rev. C EPROM Interface .............................................. 7 Applied Corrections to: DMA Controller ................................................... 7 Figure 7, SCLK VREF Filtering Scheme .................... 10 Link Ports (LVDS) ................................................ 9 Operating Conditions ........................................... 21 Timer and General-Purpose I/O ............................... 9 Added On-Chip DRAM Refresh ............................. 27 Reset and Booting ................................................. 9 Ordering Guide .................................................. 46 Clock Domains .................................................... 9 Power Domains .................................................. 10 Filtering Reference Voltage and Clocks .................... 10 Development Tools ............................................. 10 Evaluation Kit .................................................... 11 Designing an Emulator-Compatible DSP Board (Target) .......................................... 11 Additional Information ........................................ 11 Pin Function Descriptions ....................................... 12 Strap Pin Function Descriptions ................................ 20 ADSP-TS201SSpecifications .................................. 21 Operating Conditions .......................................... 21 Electrical Characteristics ....................................... 22 Package Information ........................................... 23 Absolute Maximum Ratings .................................. 23 ESD Sensitivity ................................................... 23 Timing Specifications .......................................... 24 General AC Timing .......................................... 24 Link Port Low Voltage, Differential-Signal (LVDS) Electrical Characteristics, and Timing ................ 30 Link PortData Out Timing ........................... 31 Link PortData In Timing ............................. 34 Output Drive Currents ......................................... 36 Rev. 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