TigerSHARC Embedded Processor ADSP-TS203S 1149.1 IEEE-compliant JTAG test access port for on-chip KEY FEATURES emulation 500 MHz, 2.0 ns instruction cycle rate On-chip arbitration for glueless multiprocessing 4M bits of internalon-chipDRAM memory KEY BENEFITS 25 mm 25 mm (576-ball) thermally enhanced ball grid array package Provides high performance static superscalar DSP Dual-computation blockseach containing an ALU, a multi- operations, optimized for large, demanding plier, a shifter, and a register file multiprocessor DSP applications Dual-integer ALUs, providing data addressing and pointer Performs exceptionally well on DSP algorithm and I/O manipulation benchmarks (see benchmarks in Table 1) Single-precision IEEE 32-bit and extended-precision 40-bit Supports low overhead DMA transfers between internal floating-point data formats and 8-, 16-, 32-, and 64-bit memory, external memory, memory-mapped peripherals, fixed-point data formats link ports, host processors, and other (multiprocessor) Integrated I/O includes 10-channel DMA controller, external DSPs port, two link ports, SDRAM controller, programmable flag Eases programming through extremely flexible instruction pins, two timers, and timer expired pin for system set and high-level-language-friendly architecture integration Enables scalable multiprocessing systems with low commu- nications overhead JTAG PORT DATA ADDRESS GENERATION 4M BITS INTERNAL MEMORY SOC BUS 6 32 32 INTEGER MEMORY BLOCKS INTEGER JTAG JALU KALU (PAGE CACHE) EXTERNAL 32-BIT 32-BIT 32-BIT 32-BIT 4 CROSSBAR CONNECT PORT PROGRAM SEQUENCER 32 A A A A D D D D ADDR 32 HOST J-BUS ADDR ADDR FETCH 32 MULTI- 128 DATA J-BUS DATA PROC 8 SDRAM CTRL K-BUS ADDR 32 CTRL 10 BTB C-BUS CTRL K-BUS DATA 128 ARB SOC I-BUS ADDR 32 I/F EXT DMA REQ 4 I-BUS DATA 128 DMA PC LINK PORTS S-BUS ADDR 21 4 IN 8 L0 4 128 S-BUS DATA OUT 8 IAB T 4 8 IN L1 4 OUT 8 4 128 128 X Y REGISTER REGISTER 128 128 SHIFT ALU MUL MUL ALU SHIFT FILE DAB DAB FILE 32-BIT 32-BIT 32-BIT 32-BIT COMPUTATIONAL BLOCKS Figure 1. Functional Block Diagram TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.3113 2012 Analog Devices, Inc. All rights reserved. OBSOLETEADSP-TS203S TABLE OF CONTENTS Key Features ........................................................... 1 Additional Information ........................................ 10 Key Benefits ........................................................... 1 Pin Function Descriptions ........................................ 11 General Description ................................................. 3 Strap Pin Function Descriptions ................................ 18 Dual Compute Blocks ............................................ 4 Specifications ........................................................ 20 Data Alignment Buffer (DAB) .................................. 4 Operating Conditions ........................................... 20 Dual Integer ALU (IALU) ....................................... 4 Electrical Characteristics ....................................... 21 Program Sequencer ............................................... 4 Package Information ............................................ 22 Memory ............................................................. 5 Absolute Maximum Ratings ................................... 22 External Port (Off-Chip Memory/Peripherals Interface) . 5 ESD Sensitivity ................................................... 22 DMA Controller ................................................... 7 Timing Specifications ........................................... 23 Link Ports (LVDS) ................................................ 7 Output Drive Currents ......................................... 34 Timer and General-Purpose I/O ............................... 8 Test Conditions .................................................. 35 Reset and Booting ................................................. 8 Environmental Conditions .................................... 38 Clock Domains .................................................... 8 576-Ball BGA ED Pin Configurations ......................... 39 Filtering Reference Voltage and Clocks ...................... 8 Outline Dimensions ................................................ 46 Power Domains .................................................... 9 Surface Mount Design .......................................... 46 Development Tools ............................................... 9 Ordering Guide ..................................................... 47 Related Signal Chains .......................................... 10 REVISION HISTORY 5/12Rev. C to Rev. D Added model to Ordering Guide ................................ 47 Rev. D Page 2 of 48 May 2012 OBSOLETE