MicroConverter , Multichannel a 12-Bit ADC with Embedded Flash MCU ADuC812 FEATURES APPLICATIONS Analog I/O Intelligent Sensors Calibration and Conditioning 8-Channel, High Accuracy 12-Bit ADC Battery-Powered Systems (Portable PCs, Instruments, On-Chip, 100 ppm/ C Voltage Reference Monitors) High Speed 200 kSPS Transient Capture Systems DMA Controller for High Speed ADC-to-RAM Capture DAS and Communications Systems 2 12-Bit Voltage Output DACs Control Loop Monitors (Optical Networks/Base Stations) On-Chip Temperature Sensor Function GENERAL DESCRIPTION Memory The ADuC812 is a fully integrated 12-bit data acquisition system 8K Bytes On-Chip Flash/EE Program Memory incorporating a high performance self-calibrating multichannel 640 Bytes On-Chip Flash/EE Data Memory ADC, dual DAC, and programmable 8-bit MCU (8051 instruc- 256 Bytes On-Chip Data RAM tion set compatible) on a single chip. 16M Bytes External Data Address Space 64K Bytes External Program Address Space The programmable 8051 compatible core is supported by 8K 8051 Compatible Core bytes Flash/EE program memory, 640 bytes Flash/EE data 12 MHz Nominal Operation (16 MHz Max) memory, and 256 bytes data SRAM on-chip. 3 16-Bit Timer/Counters Additional MCU support functions include Watchdog Timer, High Current Drive CapabilityPort 3 Power Supply Monitor, and ADC DMA functions. Thirty-two 9 Interrupt Sources, 2 Priority Levels 2 programmable I/O lines, I C compatible SPI and Standard Power UART Serial Port I/O are provided for multiprocessor interfaces Specified for 3 V and 5 V Operation and I/O expansion. Normal, Idle, and Power-Down Modes Normal, idle, and power-down operating modes for both the On-Chip Peripherals MCU core and analog converters allow flexible power manage- UART and SPI Serial I/O 2 ment schemes suited to low power applications. The part is 2-Wire (400 kHz I C Compatible) Serial I/O specified for 3 V and 5 V operation over the industrial tem- Watchdog Timer perature range and is available in a 52-lead, plastic quad Power Supply Monitor flatpack package. FUNCTIONAL BLOCK DIAGRAM P0.0P0.7 P1.0P1.7 P2.0P2.7 P3.0P3.7 DAC0 BUF DAC0 ADC 12-BIT AIN0 (P1.0)AIN7 (P1.7) CONTROL DAC SUCCESSIVE AIN T/H AND CONTROL APPROXIMATION MUX CALIBRATION ADC LOGIC BUF DAC1 DAC1 T0 (P3.4) MICROCONTROLLER T1 (P3.5) T2 (P1.0) 8051 BASED POWER SUPPLY 3 16-BIT MICROCONTROLLER CORE MONITOR TIMER/COUNTERS 2.5V TEMP T2EX (P1.1) REF SENSOR 8K 8 PROGRAM WATCHDOG 2-WIRE INT0 (P3.2) SPI FLASH EEPROM TIMER SERIAL I/O INT1 (P3.3) 640 8 USER ALE UART MUX V BUF FLASH EEPROM REF PSEN 256 8 USER OSC EA RAM ADuC812 C REF RESET AV AGND DV DGND XTAL1 XTAL2 RxD TxD SCLOCK MOSI/ MISO DD DD (P3.0) (P3.1) SDATA (P3.3) Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 200120 17 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ADuC812 TABLE OF CONTENTS FEATURES 1 WATCHDOG TIMER . 24 APPLICATONS . 1 POWER SUPPLY MONITOR . 24 GENERAL DESCRIPTION . 1 SERIAL PERIPHERAL INTERFACE . 25 SPECIFICATIONS 3 MISO (Master In, Slave Out Data I/O Pin) 25 ABSOLUTE MAXIMUM RATINGS 6 MOSI (Master Out, Slave In Pin) . 26 PIN CONFIGURATIONS . 6 SCLOCK (Serial Clock I/O Pin) 26 56 ORDERING GUIDE . SS (Slave Select Input Pin) 26 PIN FUNCTION DESCRIPTIONS . 7 Using the SPI Interface . 27 TERMINOLOGY 8 SPI InterfaceMaster Mode . 27 ADC SPECIFICATIONS 8 SPI InterfaceSlave Mode 27 2 Integral Nonlinearity 8 I C COMPATIBLE INTERFACE 28 Differential Nonlinearity . 8 8051 COMPATIBLE ON-CHIP PERIPHERALS 29 Offset Error . 8 Parallel I/O Ports 03 . 29 Full-Scale Error 8 Timers/Counters 29 Signal to (Noise + Distortion) Ratio 8 Timer/Counters 0 and 1 Data Registers . 31 Total Harmonic Distortion . 8 TH0 and TL0 31 DAC SPECIFICATIONS 8 TH1 and TL1 31 Relative Accuracy . 8 TIMER/COUNTERS 0 AND 1 OPERATING MODES . 32 Voltage Output Settling Time . 8 Mode 0 (13-Bit Timer/Counter) 32 Digital-to-Analog Glitch Impulse . 8 Mode 1 (16-Bit Timer/Counter) 32 ARCHITECTURE, MAIN FEATURES 9 Mode 2 (8-Bit Timer/Counter with Auto Reload) . 32 MEMORY ORGANIZATION 9 Mode 3 (Two 8-Bit Timer/Counters) 32 OVERVIEW OF MCU-RELATED SFRs . 10 Timer/Counter 2 Data Registers 33 Accumulator SFR . 10 TH2 and TL2 33 B SFR 10 RCAP2H and RCAP2L . 33 Stack Pointer SFR . 10 Timer/Counter Operation Modes . 34 Data Pointer . 10 16-Bit Autoreload Mode 34 Program Status Word SFR . 10 16-Bit Capture Mode . 34 Power Control SFR 10 UART SERIAL INTERFACE . 35 SPECIAL FUNCTION REGISTERS . 11 Mode 0 (8-Bit Shift Register Mode) . 36 ADC CIRCUIT INFORMATION 12 Mode 1 (8-Bit UART, Variable Baud Rate) 36 General Overview 12 Mode 2 (9-Bit UART with Fixed Baud Rate) 36 ADC Transfer Function . 12 Mode 3 (9-Bit UART with Variable Baud Rate) 36 Typical Operation . 12 UART Serial Port Baud Rate Generation . 36 ADCCON1(ADC Control SFR 1) . 13 Timer 1 Generated Baud Rates . 37 ADCCON2(ADC Control SFR 2) . 14 Timer 2 Generated Baud Rates . 37 ADCCON3(ADC Control SFR 3) . 14 INTERRUPT SYSTEM 38 Driving the ADC 15 Interrupt Priority 39 Voltage Reference Connections . 16 Interrupt Vectors 39 Configuring the ADC . 16 ADuC812 HARDWARE DESIGN CONSIDERATIONS 40 ADC DMA Mode . 16 Clock Oscillator . 40 DMA Mode Configuration Example . 17 External Memory Interface 40 Micro Operation during ADC DMA Mode 17 Power-On Reset Operation 41 Offset and Gain Calibration Coefficients 17 Power Supplies 41 Calibration . 18 Power Consumption . 42 NONVOLATILE FLASH MEMORY . 18 Grounding and Board Layout Recommendations . 43 Flash Memory Overview 18 OTHER HARDWARE CONSIDERATIONS . 44 Flash/EE Memory and the ADuC812 18 In-Circuit Serial Download Access 44 ADuC812 Flash/EE Memory Reliability 18 Embedded Serial Port Debugger 44 Using the Flash/EE Program Memory 19 Single-Pin Emulation Mode 45 Using the Flash/EE Data Memory . 19 Enhanced-Hooks Emulation Mode 45 ECONFlash/EE Memory Control SFR . 20 Typical System Configuration 45 Flash/EE Memory Timing . 20 QUICKSTART DEVELOPMENT SYSTEM . 45 Using the Flash/EE Memory Interface 20 DownloadIn-Circuit Serial Downloader . 45 Erase-All 20 DeBugIn-Circuit Debugger 45 Program a Byte . 20 ADSIMWindows Simulator 45 USER INTERFACE TO OTHER ON-CHIP TIMING SPECIFICATIONS . 46 ADuC812 PERIPHERALS 21 OUTLINE DIMENSIONS 56 Using the DAC . 22 Revision History 57 2 REV. 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