MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kB Flash MCU Data Sheet ADuC832 FEATURES FUNCTIONAL BLOCK DIAGRAM ANALOG I/O 12-BIT ADuC832 BUF DAC0 DAC 8-channel, 247 kSPS, 12-Bit ADC DC performance: 1 LSB INL 12-BIT AC performance: 71 dB SNR BUF DAC1 ADC0 DAC ADC1 T/H 12-BIT ADC DMA controller for high speed ADC-to-RAM capture 16-BIT 2 12-bit (monotonic) voltage output DACs MUX - DAC ADC5 Dual output PWM/- DACs ADC6 16-BIT PWM0 On-chip temperature sensor function: 3C HARDWARE - DAC ADC7 CALIBRATON MUX On-chip voltage reference 16-BIT PWM1 TEMP PWM Memory SENSOR 62 kB on-chip Flash/EE program memory 16-BIT PWM 4 kB on-chip Flash/EE data memory Flash/EE, 100 Yr retention, 100,000 cycles of endurance 8051-BASED MCU WITH ADDITIONAL PERIPHERALS 2304 bytes on-chip data RAM 62 kB FLASH/EE PROGRAM MEMORY PLL 4 kB FLASH/EE DATA MEMORY 8051-based core 2304 BYTES USER RAM 8051-compatible instruction set (16 MHz maximum) 3 16-BIT TIMERS POWER SUPPLY MON 1 REAL-TIME CLOCK WATCHDOG TIMER INTERNAL 32 kHz external crystal, on-chip programmable PLL BAND GAP OSC 2 4 PARALLEL UART, I C, AND SPI VREF 12 interrupt sources, 2 priority levels PORTS SERIAL I/O Dual data pointer V XTAL1 XTAL2 REF Extended 11-bit stack pointer Figure 1. On-chip peripherals GENERAL DESCRIPTION Time interval counter (TIC) 2 UART, I C, and SPI Serial I/O The ADuC832 is a complete, smart transducer front end, Watchdog timer (WDT), power supply monitor (PSM) integrating a high performance self-calibrating multichannel Power 12-bit ADC, dual 12-bit DACs, and programmable 8-bit MCU Specified for 3 V and 5 V operation on a single chip. Normal, idle, and power-down modes The device operates from a 32 kHz crystal with an on-chip PLL, Power-down: 25 A 3 V with wake-up timer running generating a high frequency clock of 16.78 MHz. This clock is, in turn, routed through a programmable clock divider from APPLICATIONS which the MCU core clock operating frequency is generated. Optical networkinglaser power control The microcontroller core is an 8052 and is therefore 8051 Base station systems instruction set compatible with 12 core clock periods per Precision instrumentation, smart sensors machine cycle. 62 kB of nonvolatile Flash/EE program memory are Transient capture systems provided on chip. There are also 4 kB of nonvolatile Flash/EE data DAS and communications systems memory, 256 bytes of RAM, and 2 kB of extended RAM integrated Upgrade to ADuC812 systems runs from 32 kHz on chip. External crystal with on-chip PLL. Also available: ADuC831 pin-compatible upgrade to The ADuC832 also incorporates additional analog functionality existing ADuC812 systems that require additional with two 12-bit DACs, a power supply monitor, and a band gap code or data memory runs from 1 MHz to 16 MHz reference. On-chip digital peripherals include two 16-bit - External crystal DACs, a dual-output 16-bit PWM, a watchdog timer, time interval counter, three timers/counters, Timer 3 for baud rate 2 generation, and serial I/O ports (SPI, I C, and UART). Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20022016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 02987-001ADuC832 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Initiating Calibration in Code ...................................................... 44 Applications ....................................................................................... 1 Nonvolatile Flash/EE Memory ..................................................... 45 Functional Block Diagram .............................................................. 1 Flash/EE Memory Overview .................................................... 45 General Description ......................................................................... 1 Flash/EE Memory and the ADuC832 ..................................... 45 Revision History ............................................................................... 4 ADuC832 Flash/EE Memory Reliability ................................. 45 Specif icat ions ..................................................................................... 6 Using the Flash/EE Program Memory .................................... 46 Timing Specifications ................................................................ 10 Flash/EE Program Memory Security ....................................... 47 Absolute Maximum Ratings .......................................................... 20 Using the Flash/EE Data Memory ............................................... 48 ESD Caution ................................................................................ 20 ECONFlash/EE Memory Control SFR ................................ 48 Pin Configurations and Function Descriptions ......................... 21 Example: Programming the Flash/EE Data Memory ............ 49 Typical Performance Characteristics ........................................... 26 Flash/EE Memory Timing ........................................................ 49 Terminology .................................................................................... 29 ADuC832 Configuration SFR (CFG832) ................................ 50 ADC Specifications .................................................................... 29 User Interface to Other On-Chip ADuC832 Peripherals ......... 51 DAC Specifications..................................................................... 29 DAC .............................................................................................. 51 Explanation of Typical Performance Plots .................................. 30 Using the DAC ............................................................................ 52 Memory Organization ................................................................... 31 On-Chip PLL................................................................................... 54 Flash/EE Program Memory ...................................................... 31 PLLCON (PLL Control Register) ............................................. 54 Flash/EE Data Memory ............................................................. 31 Pulse-Width Modulator (PWM) .................................................. 55 General-Purpose RAM .............................................................. 31 PWMCON (PWM Control SFR) ............................................. 55 External Data Memory (External XRAM) .............................. 32 PWM Modes of Operation............................................................ 56 Internal XRAM ........................................................................... 32 Mode 0: PWM Disabled ............................................................ 56 Special Function Registers (SFRs) ................................................ 33 Mode 1: Single Variable Resolution PWM ............................. 56 Accumulator SFR (ACC) ........................................................... 33 Mode 2: Twin 8-Bit PWM ......................................................... 56 B SFR (B) ..................................................................................... 33 Mode 3: Twin 16-Bit PWM ....................................................... 56 Stack Pointer (SP and SPH)....................................................... 33 Mode 4: Dual NRZ 16-Bit - DAC ....................................... 57 Data Pointer (DPTR) ................................................................. 33 Mode 5: Dual 8-Bit PWM ......................................................... 57 Program Status Word (PSW) .................................................... 33 Mode 6: Dual RZ 16-Bit - DAC .......................................... 57 Power Control SFR (PCON) ..................................................... 33 Serial Peripheral Interface ............................................................. 58 Special Function Registers ............................................................. 34 MISO (Master Input, Slave Output Data Pin) ............................ 58 ADC Circuit Information .............................................................. 35 MOSI (Master Output, Slave Input Pin) ................................. 58 General Overview ....................................................................... 35 SCLOCK (Serial Clock I/O Pin) .............................................. 58 ADC Transfer Function ............................................................. 35 SS (Slave Select Input Pin)......................................................... 58 Typical Operation ....................................................................... 35 Using the SPI Interface .............................................................. 59 Driving the Analog-to-Digital Converter ............................... 39 SPI InterfaceMaster Mode .................................................... 59 Voltage Reference Connections ................................................ 40 SPI InterfaceSlave Mode ........................................................ 59 2 Configuring the ADC ................................................................ 41 I C-Compatible Interface .............................................................. 60 2 ADC DMA Mode ....................................................................... 41 I C Interface SFRs ....................................................................... 60 Micro-Operation During ADC DMA Mode .......................... 42 Overview ..................................................................................... 61 ADC Offset and Gain Calibration Coefficients ..................... 42 Software Master Mode ............................................................... 61 Calibrating the ADC ...................................................................... 43 Hardware Slave Mode ................................................................ 61 Rev. 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