Low Power Precision Analog Microcontroller, ARM Cortex-M3, with Dual Sigma-Delta ADCs Silicon Anomaly ADuCM360/ADuCM361 This anomaly list describes the known bugs, anomalies, and workarounds for the ADuCM360/ADuCM361 MicroConverter Revision D silicon. The anomalies listed apply to all ADuCM360/ADuCM361 packaged material branded as follows: First Line ADuCM360 or ADuCM361 Second Line BCPZ Third Line D30 (revision identifier) Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended workarounds outlined here. ADuCM360/ADuCM361 FUNCTIONALITY ISSUES Silicon Kernel Revision Revision Silicon Identifier Identifier Chip Marking Status Anomaly Sheet No. of Reported Anomalies D 0 All silicon branded Release Rev. A 4 D30 ADuCM360/ADuCM361 PERFORMANCE ISSUES Silicon Kernel Revision Revision Silicon Identifier Identifier Chip Marking Status Anomaly Sheet No. of Reported Anomalies D 0 All silicon branded Release Rev. A 1 D30 ADuCM360/ADuCM361 SILICON FUTURE ENHANCEMENTS Silicon Kernel Revision Revision Silicon Identifier Identifier Chip Marking Status Anomaly Sheet No. of Reported Anomalies D 0 All silicon branded Release Rev. A 0 D30 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122014 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ADuCM360/ADuCM361 Silicon Anomaly PERFORMANCE ISSUES Table 1. ADC Gain = 1, ADC Input Buffers Enabled pr008 Background When ADCs are configured for Gain = 1, the PGA is disabled. ADC input buffers may be enabled or disabled when ADC gain = 1. The ADC data output accuracy is not linear and does not meet the ADC specifications when the ADC input buffers are Issue enabled. Workaround The issue is not present when ADC gain 2. When using Gain = 1, ensure the input buffers are bypassed and powered down, for example: ADCxCON 17:14 = 1111 . Related Issues None. FUNCTIONALITY ISSUES Table 2. External Interrupts in Debug Mode and Cortex-M3 in Deep Sleep Mode er007 Background The ADuCM360/ADuCM361 has various low power modes. External interrupts can wake up the Cortex-M3 core from any of these low power modes. When in debug mode, placing the ADuCM360/ADuCM361 in Mode 4 or Mode 5 forces the Cortex-M3 core into deep sleep mode, however the high power LDO, oscillator, and clocks remain active. Issue The interrupt detection unit, external interrupt 0 to 7, will not wake the Cortex-M3 core from deep sleep (Mode 4 and Mode 5) when the debug logic is active, specifically if the debug software has set either the CDBGPWRUP or CSYSPWRUP bits in the CTRL/STAT register. These are Cortex-M3 debug logic bits not visible from user code these bits can only be cleared by a write via the ARM serial wire download or a power on reset. Workaround None. Related Issues None. Table 3. Debug Mode and Deep Sleep Mode er008 Background The ADuCM360/ADuCM361 has various low power modes. When in debug mode, placing the ADuCM360/ADuCM361 in Mode 4 or Mode 5 forces the Cortex-M3 core into deep sleep mode the rest of the device remains active. Issue After serial wire debug access, the serial wire logic may prevent a complete power down of the device. The debug logic is cleared by a power cycle. Workaround Power cycle the device after serial wire debug access. Related Issues None. 2 Table 4. I C Slave not Releasing the Bus er009 2 Background When an I C read request happens, if the TX FIFO of the slave is empty, the slave must NACK the request from the master. Then it must release the bus, allowing the master to generate a STOP condition. If the TX FIFO of the slave is loaded with a byte with an MSB of 0, just on the rising edge of SCL for the ACK/NACK, the Issue slave will pull the SDA low and hold the line until the device is reset. Workaround Make sure the TX FIFO is always loaded on time by preloading TX FIFO in the preceding RX interrupt. Related Issues None. 2 Table 5. I C Clock Stretch Issue er010 2 Background Clock stretching is a feature that allows a device to halt the I C bus temporarily by holding SCL low. Register I2CxSCON Bit 6 enables clock stretching in slave mode. Register I2CxMCON Bit 3 enables clock stretching in master mode. Issue Writing to I2CxSCON Bit 6 or to I2CxMCON Bit 3 on the rising edge of SCL can cause a glitch that can be interpreted by other devices as a real clock edge and might hang the bus. Do not enable clock stretching. Workaround Related Issues None. Rev. A Page 2 of 4