3.0 kV RMS 5-Channel Digital Isolators Data Sheet ADuM150N/ADuM151N/ADuM152N FEATURES FUNCTIONAL BLOCK DIAGRAMS High common-mode transient immunity: 100 kV/s V 1 ADu M 15 0N 16 V DD1 DD2 High robustness to radiated and conducted noise V V IA 2 ENCO DE DECO DE 15 OA Low propagation delay V V 3 ENCO DE DECO DE 14 IB OB 13 ns maximum for 5 V operation V V 4 ENCO DE DECO DE 13 IC OC 15 ns maximum for 1.8 V operation V V 5 ENCO DE DECO DE 12 150 Mbps maximum guaranteed data rate ID OD Safety and regulatory approvals (pending) V 6 ENCO DE DECO DE 11 V IE OE UL recognition: 3000 V rms for 1 minute per UL 1577 NI C 7 10 NI C CSA Component Acceptance Notice 5A GND 8 9 GND 1 2 VDE certificate of conformity Figure 1. ADuM150N Functional Block Diagram DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 V = 565 V peak IORM V V 1 ADu M 15 1N 16 DD1 DD2 CQC certification per GB4943.1-2011 V V 2 ENCO DE DECO DE 15 IA OA Low dynamic power consumption V 3 ENCO DE DECO DE 14 V IB OB 1.8 V to 5 V level translation V 4 ENCO DE DECO DE 13 V High temperature operation: 125C IC OC Fail-safe high or low options V V ID 5 ENCO DE DECO DE 12 OD 16-lead, RoHS compliant, narrow-body SOIC package V V 6 DECO DE ENCO DE 11 OE IE APPLICATIONS NI C NI C 7 10 GND GND 8 9 1 2 General-purpose multichannel isolation Serial peripheral interface (SPI)/data converter isolation Figure 2. ADuM151N Functional Block Diagram Industrial field bus isolation GENERAL DESCRIPTION V 1 ADu M 15 2N 16 V DD1 DD2 1 V 2 15 V IA ENCO DE DECO DE OA The ADuM150N/ADuM151N/ADuM152N are 5-channel V V digital isolators based on Analog Devices, Inc., iCoupler 3 ENCO DE DECO DE 14 IB OB technology. Combining high speed, complementary metal-oxide V V 4 ENCO DE DECO DE 13 IC OC semiconductor (CMOS) and monolithic air core transformer V V 5 DECO DE ENCO DE 12 OD ID technology, these isolation components provide outstanding V 6 DECO DE ENCO DE 11 V OE IE performance characteristics superior to alternatives such as NI C 7 10 NI C optocoupler devices and other integrated couplers. The GND 8 9 GND 1 2 maximum propagation delay is 13 ns with a pulse width Figure 3. ADuM152N Functional Block Diagram distortion of less than 4.5 ns at 5 V operation. Channel to channel matching of propagation delay is tight at 4.0 ns maximum. The ADuM150N/ADuM151N/ADuM152N data channels are independent and are available in a variety of configurations Unlike other optocoupler alternatives, dc correctness is ensured with a withstand voltage rating of 3.0 kV rms (see the Ordering in the absence of input logic transitions. Two different fail-safe Guide). The devices operate with the supply voltage on either options are available by which the outputs transition to a predeter- side ranging from 1.7 V to 5.5 V, providing compatibility with mined state when the input power supply is not applied. lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. 1 Protected by U.S. Patents 5,952,849 6,873,065 6,903,578 and 7,075,329. Other patents are pending. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 14531-003 14531-002 14531-001ADuM150N/ADuM151N/ADuM152N Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Recommended Operating Conditions .................................... 12 Applications ....................................................................................... 1 Absolute Maximum Ratings ......................................................... 13 General Description ......................................................................... 1 ESD Caution................................................................................ 13 Functional Block Diagrams ............................................................. 1 Pin Configurations and Function Descriptions ......................... 14 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 17 Specif icat ions ..................................................................................... 3 Theory of Operation ...................................................................... 19 Electrical Characteristics5 V Operation................................ 3 Applications Information .............................................................. 20 Electrical Characteristics3.3 V Operation ............................ 5 PCB Layout ................................................................................. 20 Electrical Characteristics2.5 V Operation ............................ 7 Propagation Delay Related Parameters ................................... 20 Electrical Characteristics1.8 V Operation ............................ 9 Jitter Measurement ..................................................................... 20 Insulation and Safety Related Specifications .......................... 11 Insulation Lifetime ..................................................................... 20 Package Characteristics ............................................................. 11 Outline Dimensions ....................................................................... 22 Regulatory Information ............................................................. 11 Ordering Guide .......................................................................... 22 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics ............................................................................ 12 REVISION HISTORY 7/2019Rev. 0 to Rev. A Changes to Table 11 ........................................................................ 11 8/2016Revision 0: Initial Version Rev. A Page 2 of 22