3.75 kV, 6-Channel, SPIsolator Digital Isolator for SPI with Delay Clock Data Sheet ADuM3150 FEATURES FUNCTIONAL BLOCK DIAGRAM Supports up to 40 MHz SPI clock speed in delay clock mode V 1 20 V DD1 ADuM3150 DD2 Supports up to 17 MHz SPI clock speed in 4-wire mode GND 2 19 GND 1 2 ENCODE DECODE 4 high speed, low propagation delay, SPI signal isolation MCLK 3 18 SCLK ENCODE DECODE channels MO 4 17 SI DECODE ENCODE 2 data channels at 250 kbps SO MI 5 16 ENCODE DECODE Delayed compensation clock line MSS 15 SSS 6 20-lead SSOP with 5.1 mm creepage High temperature operation: 125C V 7 14 V IA OA CONTROL CONTROL BLOCK BLOCK High common-mode transient immunity: >25 kV/s V 8 13 V OB IB Safety and regulatory approvals DCLK 9 CLK 12 NIC DELAY UL recognition per UL 1577 GND GND 10 11 1 2 3750 V rms for 1 minute CSA Component Acceptance Notice 5A Figure 1. VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 V = 565 V peak IORM APPLICATIONS Industrial programmable logic controllers (PLC) Sensor isolation GENERAL DESCRIPTION 1 The ADuM3150 is a 6-channel SPIsolator digital isolator Table 1. Related Products optimized for isolated serial peripheral interfaces (SPIs). Based Product Description on the Analog Devices, Inc., iCoupler chip scale transformer ADuM3151/ADuM3152/ 3.75 kV, multichannel SPI isolator technology, the low propagation delay in the CLK, MO/SI, ADuM3153 SS MI/SO, and SPI bus signals supports SPI clock rates of up to ADuM3154 3.75 kV, multiple slave SPI isolator 17 MHz. These channels operate with 14 ns propagation delay ADuM4150 5 kV, high speed, clock delayed and 1 ns jitter to optimize timing for SPI. SPIsolator ADuM4151/ADuM4152/ 5 kV, multichannel SPI isolator The ADuM3150 isolator also provides two additional independent ADuM4153 low data rate isolation channels, one channel in each direction. ADuM4154 5 kV, multiple slave SPI isolator Data in the slow channels is sampled and serialized for a 250 kbps data rate with 2.5 s of jitter. The ADuM3150 supports a delay clock output on the master side of the device. This output can be used with an additional clocked port on the master to support 40 MHz clock performance. See the Delay Clock section for more information. 1 Protected by U.S. Patents 5,952,849 6,873,065 6,262,600 and 7,075,329. Other patents are pending. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 12367-001ADuM3150 Data Sheet TABLE OF CONTENTS Features........................................................................................... 1 Recommended Operating Conditions ................................... 12 Applications ................................................................................... 1 Absolute Maximum Ratings ....................................................... 13 Functional Block Diagram ............................................................ 1 ESD Caution............................................................................. 13 General Description ...................................................................... 1 Pin Configuration and Function Descriptions.......................... 14 Revision History ............................................................................ 2 Typical Performance Characteristics.......................................... 15 Specifications ................................................................................. 3 Applications Information............................................................ 16 Electrical Characteristics5 V Operation .............................. 3 Introduction ............................................................................. 16 Electrical Characteristics3.3 V Operation ........................... 5 Printed Circuit Board (PCB) Layout ...................................... 17 Electrical CharacteristicsMixed 5 V/3.3 V Operation ........ 7 Propagation Delay Related Parameters .................................. 18 Electrical CharacteristicsMixed 3.3 V/5 V Operation ........ 9 DC Correctness and Magnetic Field Immunity .................... 18 Package Characteristics ........................................................... 11 Power Consumption................................................................ 19 Regulatory Information........................................................... 11 Insulation Lifetime .................................................................. 19 Insulation and Safety Related Specifications ......................... 11 Outline Dimensions .................................................................... 21 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Ordering Guide........................................................................ 21 Characteristics ......................................................................... 12 REVISION HISTORY 7/2017Rev. B to Rev. C Changes to Output Voltages, Logic High Parameter, Table 5 and Output Voltages, Logic Low Parameter, Table 5...........................6 Changes to Output Voltages, Logic High Parameter, Table 7 and Output Voltages, Logic Low Parameter, Table 7...........................8 Changes to Output Voltages, Logic High Parameter, Table 9 and Output Voltages, Logic Low Parameter, Table 9.........................10 Change to Pin 3, Direction Column, Table 17............................14 8/2016Rev. A to Rev. B Changes to Figure 11 ....................................................................17 3/2015Rev. 0 to Rev. A Changes to Features Section and Table 1 ......................................1 Changes to Table 3 ..........................................................................4 Changes to Table 5 ..........................................................................6 Changes to Table 7 ..........................................................................8 Changes to Table 9 ........................................................................10 Changes to Table 10, Regulatory Information Section, and Table 11..........................................................................................11 Changes to Table 13 and Figure 2................................................12 Changes to Figure 4 to Figure 7 ...................................................15 Changes to High Speed Channels Section ..................................16 Changes to Power Consumption Section ...................................19 7/2014Revision 0: Initial Version Rev. C Page 2 of 21