X-On Electronics has gained recognition as a prominent supplier of ADUM4135BRWZ Gate Drivers across the USA, India, Europe, Australia, and various other global locations. ADUM4135BRWZ Gate Drivers are a product manufactured by Analog Devices. We provide cost-effective solutions for Gate Drivers, ensuring timely deliveries around the world.

ADUM4135BRWZ Analog Devices

ADUM4135BRWZ electronic component of Analog Devices
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Part No.ADUM4135BRWZ
Manufacturer: Analog Devices
Category: Gate Drivers
Description: Gate Drivers Isolated Half-bridge Gate Driver
Datasheet: ADUM4135BRWZ Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 9.2284 ea
Line Total: USD 9.23

Availability - 38
Ship by Tue. 30 Jul to Fri. 02 Aug
MOQ: 1  Multiples: 1
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23
Ship by Tue. 30 Jul to Fri. 02 Aug
MOQ : 1
Multiples : 1
1 : USD 9.4243
10 : USD 8.2242
30 : USD 7.4907
100 : USD 6.6011

   
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We are delighted to provide the ADUM4135BRWZ from our Gate Drivers category, at competitive rates not only in the United States, Australia, and India, but also across Europe and beyond. A long established and extensive electronic component distribution network has enhanced our global reach and dependability, ensuring cost savings through prompt deliveries worldwide. Client satisfaction is at the heart of our business, where every component counts and every customer matters. Our technical service team is ready to assist you. From product selection to after-sales support, we strive to deliver a seamless and satisfying experience. Are you ready to experience the best in electronic component distribution? Contact X-ON Electronics today and discover why X-On are a preferred choice for the ADUM4135BRWZ and other electronic components in the Gate Drivers category and beyond.

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Single-/Dual-Supply, High Voltage Isolated IGBT Gate Driver with Miller Clamp Data Sheet ADuM4135 FEATURES GENERAL DESCRIPTION 4 A peak drive output capability The ADuM4135 is a single-channel gate driver specifically Output power device resistance: <1 optimized for driving insulated gate bipolar transistors Desaturation protection (IGBTs). Analog Devices, Inc., iCoupler technology provides Isolated desaturation fault reporting isolation between the input signal and the output gate drive. Soft shutdown on fault The ADuM4135 includes a Miller clamp to provide robust Miller clamp output with gate sense input IGBT turn-off with a single-rail supply when the gate voltage Isolated fault and ready functions drops below 2 V (typical). Operation with unipolar or bipolar Low propagation delay: 55 ns typical secondary supplies is possible, with or without the Miller clamp Minimum pulse width: 50 ns operation. Operating temperature range: 40C to +125C Output voltage range to 30 V The Analog Devices chip scale transformers also provide Input voltage range from 2.5 V to 6 V isolated communication of control information between the Output and input undervoltage lockout (UVLO) high voltage and low voltage domains of the chip. Information Creepage distance: 7.8 mm minimum on the status of the chip can be read back from dedicated 100 kV/s common-mode transient immunity (CMTI) outputs. Control of resetting the device after a fault on the 20 year lifetime for 600 V rms or 1092 V dc working voltage secondary is performed on the primary side of the device. Safety and regulatory approvals Integrated onto the ADuM4135 is a desaturation detection 5 kV ac for 1 minute per UL 1577 circuit that provides protection against high voltage short- CSA Component Acceptance Notice 5A circuit IGBT operation. The desaturation protection contains DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 noise reducing features such as a 370 ns (typical) masking time V = 849 V peak (reinforced/basic) IORM after a switching event to mask voltage spikes due to initial turn-on. An internal 537 A (typical) current source allows low APPLICATIONS device count and the internal blanking switch allows the MOSFET/IGBT gate drivers addition of an external current source if more noise immunity PV inverters is needed. Motor drives Power supplies The secondary UVLO is set to 11.67 V (typical) with common IGBT threshold levels taken into consideration. FUNCTIONAL BLOCK DIAGRAM 16 V V 1 SS2 SS1 2V TSD 1 ADuM4135 2 V + 2 I 2 CLAMP 3 LOGIC 15 GATE SENSE V I UVLO READY 4 14 V OUT ON MASTER MASTER 2 LOGIC ENCODE DECODE LOGIC 1 13 V DD2 FAULT 5 PRIMARY SECONDARY 12 V OUT OFF 1 DECODE ENCODE 11 GND 9V 2 RESET 6 2 V 7 DD1 1 10 DESAT V 8 SS1 9 V SS2 1 UVLO 2 NOTES 1. GROUNDS ON PRIMARY AND SECONDARY SIDE ARE ISOLATED FROM EACH OTHER. Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20152020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 13082-001ADuM4135 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution ..................................................................................7 Applications ...................................................................................... 1 Pin Configuration and Function Descriptions .............................8 General Description ......................................................................... 1 Typical Performanace Characteristics ............................................9 Functional Block Diagram .............................................................. 1 Applications Information ............................................................. 12 Revision History ............................................................................... 2 PCB Layout ................................................................................. 12 Specifications .................................................................................... 3 Propagation Delay Related Parameters ................................... 12 Electrical Characteristics ............................................................. 3 Protection Features .................................................................... 12 Package Characteristics ............................................................... 5 Power Dissipation ...................................................................... 14 Regulatory Information ............................................................... 5 DC Correctness and Magnetic Field Immunity .......................... 15 Insulation and Safety Related Specifications ............................ 5 Insulation Lifetime ..................................................................... 15 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Typical Application.................................................................... 16 Characteristics .............................................................................. 6 Outline Dimensions ....................................................................... 17 Recommended Operating Conditions ...................................... 6 Ordering Guide .......................................................................... 17 Absolute Maximum Ratings ........................................................... 7 REVISION HISTORY 7/2020Rev. C to Rev. D 7/2018Rev. B to Rev. C Changes to Features Section and General Description Section ....... 1 Changes to Table 7 ............................................................................ 7 Changes to Electrical Characteristics Section and Table 1 ......... 3 Added Note 3, Table 7 Renumbered Sequentially ....................... 7 Change to Figure 24 ....................................................................... 14 Changes to Regulatory Information Section and Table 3 .......... 5 Changes to Table 6 ........................................................................... 6 Changes to Supply Voltages Parameter and Endnote 2, Table 7 ..... 7 3/2016Rev. A to Rev. B Changes to Table 10 ......................................................................... 8 Change to Figure 7 ............................................................................ 9 Changes to Figure 8 .......................................................................... 9 Changes to Figure 18 ..................................................................... 11 Changes to Figure 12 Caption and Figure 13 ............................. 10 Changes to Fault Reporting Section and Desaturation 9/2015Rev. 0 to Rev. A Detection Section ............................................................................ 12 Changes to Features Section ............................................................ 1 Changes to Figure 21, Miller Clamp Section, and Thermal Changed TA to TJ ............................................................................... 3 Shutdown Section ........................................................................... 13 Added Common-Mode Transient Immunity (CMTI) Change to DC Correctness and Magnetic Field Immunity Parameter, Table 1 ............................................................................ 4 Section .............................................................................................. 15 Changes to Table 3 and Table 4 ...................................................... 5 Changes to Table 6 ............................................................................ 6 Changes to Table 7 ............................................................................ 7 Changes to Figure 16 Caption and Figure 17 Caption ............. 11 Changes to Fault Reporting Section ............................................ 12 Change to Figure 28 ....................................................................... 16 7/2015Revision 0: Initial Version Rev. D Page 2 of 17

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