3-Axis, 2 g/4 g/8 g/16 g Ultralow Power Digital MEMS Accelerometer Data Sheet ADXL344 FEATURES GENERAL DESCRIPTION Multipurpose accelerometer with 10- to 13-bit resolution for The ADXL344 is a versatile 3-axis, digital-output, low g MEMS use in a wide variety of applications accelerometer. Selectable measurement range and bandwidth and 2 Digital output accessible via SPI (3- and 4-wire) and I C configurable, built-in motion detection make it suitable for sensing Built-in motion detection features make tap, double-tap, acceleration in a wide variety of applications. Robustness to activity, inactivity, orientation, and free-fall detection 10,000 g of shock and a wide temperature range (40C to +85C) trivial enable use of the accelerometer even in harsh environments. User-adjustable thresholds The ADXL344 measures acceleration with high resolution (13-bit) Interrupts independently mappable to two interrupt pins measurement at up to 16 g. Digital output data is formatted as Low power operation down to 23 A and embedded FIFO for 16-bit twos complement and is accessible through either a SPI reducing overall system power 2 (3- or 4-wire) or I C digital interface. The ADXL344 can Wide supply and I/O voltage range: 1.7 V to 2.75 V measure the static acceleration of gravity in tilt-sensing appli- Wide operating temperature range (40C to +85C) cations, as well as dynamic acceleration resulting from motion 10,000 g shock survival or shock. Its high resolution (3.9 mg/LSB) enables measurement Small, thin Pb free, RoHS compliant 3 mm 3 mm 0.95 mm of inclination changes less than 1.0. LGA package Several special sensing functions are provided. Activity and inactivity sensing detect the presence or lack of motion. Tap APPLICATIONS sensing detects single and double taps in any direction. Free-fall Handsets sensing detects if the device is falling. Orientation detection Gaming and pointing devices reports four- and six-position orientation and can trigger an Hard disk drive (HDD) protection interrupt upon change in orientation. These functions can be mapped individually to either of two interrupt output pins. An integrated memory management system with a 32-level first in, first out (FIFO) buffer can be used to store data to minimize host processor activity and lower overall system power consumption. The ADXL344 is supplied in a small, thin, 3 mm 3 mm 0.95 mm, 16-terminal, plastic package. FUNCTIONAL BLOCK DIAGRAM V V S DD I/O ADXL344 POWER MANAGEMENT INT1 CONTROL SENSE ADC AND DIGITAL ELECTRONICS INTERRUPT FILTER 3-AXIS LOGIC INT2 SENSOR SDA/SDI/SDIO 32-LEVEL SERIAL I/O SDO/ALT FIFO ADDRESS SCL/SCLK GND CS Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2012 Analog Devices, Inc. All rights reserved. 10628-001ADXL344 Data Sheet TABLE OF CONTENTS Register Definitions ................................................................... 21 Features .............................................................................................. 1 Applications Information .............................................................. 27 Applications ....................................................................................... 1 Power Supply Decoupling ......................................................... 27 General Description ......................................................................... 1 Mechanical Considerations for Mounting .............................. 27 Functional Block Diagram .............................................................. 1 Tap Detection .............................................................................. 27 Revision History ............................................................................... 2 Improved Tap Detection............................................................ 28 Specifications ..................................................................................... 3 Tap Sign ....................................................................................... 28 Absolute Maximum Ratings ............................................................ 5 Threshold .................................................................................... 29 Thermal Resistance ...................................................................... 5 Link Mode ................................................................................... 29 Package Information .................................................................... 5 Sleep Mode vs. Low Power Mode............................................. 29 ESD Caution .................................................................................. 5 Offset Calibration ....................................................................... 29 Pin Configuration and Function Descriptions ............................. 6 Using Self-Test ............................................................................ 30 Typical Performance Characteristics ............................................. 7 Orientation Sensing ................................................................... 31 Theory of Operation ...................................................................... 10 Data Formatting of Upper Data Rates ..................................... 32 Power Sequencing ...................................................................... 10 Noise Performance ..................................................................... 33 Power Savings.............................................................................. 11 Operation at Voltages Other Than 2.6 V ................................ 33 Serial Communications ................................................................. 12 Offset Performance at Lowest Data Rates ............................... 34 SPI ................................................................................................. 12 2 Axes of Acceleration Sensitivity ............................................... 35 I C ................................................................................................. 15 Layout and Design Recommendations ................................... 36 Interrupts ..................................................................................... 17 Outline Dimensions ....................................................................... 37 FIFO ............................................................................................. 18 Ordering Guide .......................................................................... 37 Self-Test ........................................................................................ 19 Register Map .................................................................................... 20 REVISION HISTORY 4/12Revision 0: Initial Version Rev. 0 Page 2 of 40