Low Noise, Low Drift, Low Power, 3-Axis MEMS Accelerometers Data Sheet ADXL354/ADXL355 FEATURES FUNCTIONAL BLOCK DIAGRAMS V V 1P8ANA 1P8DIG RANGE Hermetic package offers optimal long-term stability 0 g offset vs. temperature (all axes): 0.15 mg/C maximum LDO POWER V SUPPLY LDO Ultralow noise spectral density, all axes: 22.5 g/Hz MANAGEMENT X Low power, V (LDO regulator enabled) OUT SUPPLY ANALOG ADXL354 in measurement mode: 150 A ST1 Y OUT FILTER 3-AXIS ADXL355 in measurement mode: 200 A ST2 SENSOR OUT CONTROL LOGIC ADXL354/ADXL355 in standby mode: 21 A STBY TEMP TEMP ADXL354 ADXL354 has user adjustable analog output bandwidth SENSOR V DDIO ADXL355 digital output features 2 V V Digital SPI and I C interfaces supported SSIO SS 20-bit ADC Figure 1. ADXL354 Data interpolation routine for synchronous sampling V V V 1P8ANA 1P8DIG DDIO Programmable high- and low-pass digital filters POWER LDO MANAGEMENT Electromechanical self test V LDO SUPPLY ADXL355 Integrated temperature sensor ADC INT1 CONTROL Voltage range options INT2 DIGITAL ADC ANALOG LOGIC FILTER FILTER DRDY V with internal regulators: 2.25 V to 3.6 V SUPPLY 3-AXIS ADC CS/SCL SENSOR SCLK/V V , V with internal LDO regulator bypassed: 1.8 V SSIO 1P8ANA 1P8DIG TEMP SERIAL ADC FIFO MOSI/SDA SENSOR I/O typical 10% MISO/ASEL Operating temperature range: 40C to +125C V V SSIO SS 14-terminal, 6 mm 5.6 mm 2.2 mm, LCC package Figure 2. ADXL355 APPLICATIONS Inertial measurement units (IMUs)/attitude and heading reference systems (AHRSs) Platform stabilization systems Structural health monitoring Seismic imaging Tilt sensing Robotics Condition monitoring GENERAL DESCRIPTION The analog output ADXL354 and the digital output ADXL355 Highly integrated in a compact form factor, the low power are low noise density, low 0 g offset drift, low power, 3-axis ADXL355 is ideal in an Internet of Things (IoT) sensor node accelerometers with selectable measurement ranges. The and other wireless product designs. ADXL354B supports the 2 g and 4 g ranges, the ADXL354C The ADXL355 multifunction pin names may be referenced by supports the 2 g and 8 g ranges, and the ADXL355 supports their relevant function only for either the serial peripheral the 2 g, 4 g, and 8 g ranges. The ADXL354/ADXL355 offer 2 interface (SPI) or I C interface. industry leading noise, minimal offset drift over temperature, and long-term stability enabling precision applications with minimal calibration. 1 Protected by U.S. Patents 8,472,270 9,041,462 8,665,627 8,917,099 6,892,576 9,297,825 and 7,956,621. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162020 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 14205-002 14205-001ADXL354/ADXL355 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DRDY Pin .................................................................................... 29 Applications ....................................................................................... 1 FIFO FULL ................................................................................. 29 Functional Block Diagrams ............................................................. 1 FIFO OVR .................................................................................. 29 General Description ......................................................................... 1 Activity ......................................................................................... 29 Revision History ............................................................................... 3 NVM BUSY ............................................................................... 29 Specificat ions ..................................................................................... 4 External Synchronization and Interpolation .......................... 29 Analog Output for the ADXL354 ............................................... 4 ADXL355 Register Map ................................................................. 32 Digital Output for the ADXL355 ............................................... 5 Register Definitions........................................................................ 33 SPI Digital Interface Characteristics for the ADXL355 .......... 7 Analog Devices ID Register ...................................................... 33 2 I C Digital Interface Characteristics for the ADXL355 ........... 8 Analog Devices MEMS ID Register ......................................... 33 Absolute Maximum Ratings ............................................................ 9 Device ID Register ..................................................................... 33 Thermal Resistance ...................................................................... 9 Product Revision ID Register ................................................... 33 Recommended Soldering Profile ............................................... 9 Status Register ............................................................................. 33 ESD Caution .................................................................................. 9 FIFO Entries Register ................................................................ 34 Pin Configurations and Function Descriptions ......................... 10 Temperature Data Registers ...................................................... 34 Typical Performance Characteristics ........................................... 12 X-Axis Data Registers ................................................................ 34 Root Allan Variance (RAV) ADXL355 Characteristics ......... 20 Y-Axis Data Registers ................................................................ 35 Theory of Operation ...................................................................... 21 Z-Axis Data Registers ................................................................ 35 Applications Information .............................................................. 22 FIFO Access Register ................................................................. 36 Analog Output ............................................................................ 22 X-Axis Offset Trim Registers .................................................... 36 Digital Output ............................................................................. 22 Y-Axis Offset Trim Registers .................................................... 36 Axes of Acceleration Sensitivity ............................................... 23 Z-Axis Offset Trim Registers .................................................... 37 Power Sequencing ...................................................................... 23 Activity Enable Register ............................................................ 37 Power Supply Description ......................................................... 23 Activity Threshold Registers ..................................................... 37 Overrange Protection ................................................................. 23 Activity Count Register ............................................................. 37 Self Test ........................................................................................ 23 Filter Settings Register ............................................................... 38 Filter ............................................................................................. 24 FIFO Samples Register .............................................................. 38 Serial Communications ................................................................. 26 Interrupt Pin (INTx) Function Map Register......................... 38 SPI Protocol ................................................................................. 26 Data Synchronization ................................................................ 39 2 SPI Bus Sharing ........................................................................... 26 I C Speed, Interrupt Polarity, and Range Register ................. 39 2 I C Protocol ................................................................................. 27 Power Control Register ............................................................. 39 Reading Acceleration or Temperature Data from the Interface Self Test Register ......................................................................... 40 ....................................................................................................... 27 Reset Register .............................................................................. 40 FIFO ................................................................................................. 28 PCB Footprint Pattern ................................................................... 41 Interrupts ......................................................................................... 29 Outline Dimensions ....................................................................... 42 DATA RDY ................................................................................. 29 Ordering Guide .......................................................................... 42 Rev. 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