Blackfin Embedded Processor ADSP-BF534/ADSP-BF536/ADSP-BF537 FEATURES PERIPHERALS Up to 600 MHz high performance Blackfin processor IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and ADSP-BF537 only) Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter Controller area network (CAN) 2.0B interface RISC-like register and instruction model for ease of Parallel peripheral interface (PPI), supporting ITU-R 656 programming and compiler-friendly support video data formats Advanced debug, trace, and performance monitoring 2 dual-channel, full-duplex synchronous serial ports 2 (SPORTs), supporting 8 stereo I S channels Wide range of operating voltages (see Operating Conditions on Page 23) 12 peripheral DMAs, 2 mastered by the Ethernet MAC Qualified for Automotive Applications (see Automotive Prod- 2 memory-to-memory DMAs with external request lines ucts on Page 66) Event handler with 32 interrupt inputs Programmable on-chip voltage regulator Serial peripheral interface (SPI) compatible 182-ball and 208-ball CSP BGA packages 2 UARTs with IrDA support 2-wire interface (TWI) controller MEMORY Eight 32-bit timer/counters with PWM support Up to 132K bytes of on-chip memory Real-time clock (RTC) and watchdog timer Instruction SRAM/cache and instruction SRAM 32-bit core timer Data SRAM/cache plus additional dedicated data SRAM 48 general-purpose I/Os (GPIOs), 8 with high current drivers Scratchpad SRAM (see Table 1 on Page 3 for available On-chip PLL capable of frequency multiplication memory configurations) Debug/JTAG interface External memory controller with glueless support for SDRAM and asynchronous 8-bit and 16-bit memories Flexible booting options from external flash, SPI and TWI memory or from SPI, TWI, and UART host devices Memory management unit providing memory protection VOLTAGE REGULATOR JTAG TEST AND EMULATION PERIPHERAL ACCESS BUS WATCHDOG TIMER RTC INTERRUPT CAN CONTROLLER B TWI PORT J SPORT0 L1 L1 DMA INSTRUCTION DATA SPORT1 CONTROLLER MEMORY GPIO MEMORY PORT G PPI UART0-1 DMA CORE BUS EXTERNAL ACCESS BUS GPIO SPI PORT F EXTERNAL PORT TIMER7-0 FLASH, SDRAM CONTROL ETHERNET MAC GPIO 16 (See Table 1) PORT H BOOT ROM Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. J Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2014 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Technical Support www.analog.com DMA EXTERNAL BUSADSP-BF534/ADSP-BF536/ADSP-BF537 TABLE OF CONTENTS Features ................................................................. 1 Booting Modes ................................................... 16 Memory ................................................................ 1 Instruction Set Description .................................... 17 Peripherals ............................................................. 1 Development Tools .............................................. 17 General Description ................................................. 3 Additional Information ........................................ 18 Portable Low Power Architecture ............................. 3 Related Signal Chains ........................................... 18 System Integration ................................................ 3 Pin Descriptions .................................................... 19 Blackfin Processor Peripherals ................................. 3 Specifications ........................................................ 23 Blackfin Processor Core .......................................... 4 Operating Conditions ........................................... 23 Memory Architecture ............................................ 5 Electrical Characteristics ....................................... 25 DMA Controllers .................................................. 8 Absolute Maximum Ratings ................................... 29 Real-Time Clock ................................................... 9 ESD Sensitivity ................................................... 29 Watchdog Timer .................................................. 9 Package Information ............................................ 29 Timers ............................................................... 9 Timing Specifications ........................................... 30 Serial Ports (SPORTs) .......................................... 10 Output Drive Currents ......................................... 50 Serial Peripheral Interface (SPI) Port ....................... 10 Test Conditions .................................................. 52 UART Ports ...................................................... 10 Thermal Characteristics ........................................ 56 Controller Area Network (CAN) ............................ 11 182-Ball CSP BGA Ball Assignment ........................... 57 TWI Controller Interface ...................................... 11 208-Ball CSP BGA Ball Assignment ........................... 60 10/100 Ethernet MAC .......................................... 11 Outline Dimensions ................................................ 63 Ports ................................................................ 12 Surface-Mount Design .......................................... 65 Parallel Peripheral Interface (PPI) ........................... 12 Automotive Products .............................................. 66 Dynamic Power Management ................................ 13 Ordering Guide ..................................................... 67 Voltage Regulation .............................................. 14 Clock Signals ..................................................... 15 REVISION HISTORY 2/14Rev. I to Rev. J Corrected typographical error from Three 16-bit MACs to Two 16-bit MACs in Features ............................................ 1 Updated Development Tools .................................... 17 Added t parameter to Serial Port Timing ................ 38 HDRE Added footnotes in Serial Port Timing ........................ 38 Rev. J Page 2 of 68 February 2014