12-Bit Serial Input a Multiplying D/A Converter DAC8043A FUNCTIONAL BLOCK DIAGRAM FEATURES Compact SOIC, and TSSOP Packages True 12-Bit Accuracy DAC8043A 5 V Operation <10 A V R DD FB Fast 3-Wire Serial Input V I DAC REF OUT Fast 1 s Settling Time 12 2.4 MHz 4-Quadrant Multiply BW Pin-for-Pin Upgrade for DAC8043 LD DAC REG Standard and Rotated Pinout 12 APPLICATIONS GND CLK 12-BIT SHIFT Ideal for PLC Applications in Industrial Control REGISTER SRI Programmable Amplifiers and Attenuators Digitally Controlled Calibration and Filters Motion Control Systems 0.5 GENERAL DESCRIPTION T = +25 C, +85 C, 40 C A 0.4 The DAC8043A is an improved high accuracy 12-bit multiply- V = +5V DD V = 10V ing digital-to-analog converter in space-saving 8-lead packages. REF 0.3 Featuring serial input, double buffering and excellent analog 0.2 performance, the DAC8043A is ideal for applications where PC 0.1 board space is at a premium. Improved linearity and gain error 0 performance permit reduced parts count through the elimina- tion of trimming components. Separate input clock and load 0.1 DAC control lines allow full user control of data loading and 0.2 analog output. 0.3 The circuit consists of a 12-bit serial-in/parallel-out shift regis- 0.4 ter, a 12-bit DAC register, a 12-bit CMOS DAC and control logic. Serial data is clocked into the input register on the rising 0.5 0 512 1024 1536 2048 2560 3072 3584 4096 edge of the CLOCK pulse. When the new data word has been CODE clocked in, it is loaded into the DAC register with the LD input Figure 1. Integral Nonlinearity Error vs. Code pin. Data in the DAC register is converted to an output current by the D/A converter. Consuming only 10 A from a single 5 V power supply, the DAC8043A is the ideal low power, small size, high performance solution to many application problems. The DAC8043A is specified over the extended industrial (40C to +85C) temperature range. DAC8043A is available in a PDIP package, and the low profile 1.75 mm height SOIC-8 surface mount packages. The DAC8043AFRU is available for ultra-compact applications in a thin 1.1 mm TSSOP-8 package. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: DAC8043ASPECIFICATIONS ELECTRICAL CHARACTERISTICS ( V = 5 V, V = 10 V, 40 C < T < +85 C, unless otherwise noted.) DD REF A Parameter Symbol Condition E Grade F Grade Unit STATIC PERFORMANCE Resolution N 12 12 Bits Relative Accuracy INL 0.5 1.0 LSB max Differential Nonlinearity DNL All Grades Monotonic to 12 Bits 0.5 1.0 LSB max 1 Gain Error G T = 25C, Data = FFF 1.0 2.0 LSB max FSE A H T = 40C, +85C, Data = FFF 2.0 2.0 LSB max A H 2 Gain Tempco TCG I Pin Measured 5 5 ppm/C max FS OUT Output Leakage Current I Data = 000 , I Pin Measured 5 5 nA max LKG H OUT T = 40C, +85C, Data = 000 , I Pin Measured 25 25 nA max A H OUT 3 Zero-Scale Error I Data = 000 0.03 0.03 LSB max ZSE H T = 40C, +85C, Data = 000 0.15 0.15 LSB max A H REFERENCE INPUT Input Resistance R Absolute Tempco < 50 ppm/C 7/15 7/15 k min/max REF 2 Input Capacitance C 55 pF typ REF ANALOG OUTPUT 2 Output Capacitance C Data = 000 25 25 pF typ OUT H Data = FFF 30 30 pF typ H DIGITAL INPUTS Digital Input Low V 0.8 0.8 V max IL Digital Input High V 2.4 2.4 V min IH Input Leakage Current I V = 0 V to 5 V 0.001/1 0.001/1 A typ/max IL LOGIC 2 Input Capacitance C V = 0 V 10 10 pF max IL LOGIC 2, 4 INTERFACE TIMING Data Setup t 10 10 ns min DS Data Hold t 55 ns min DH Clock Width High t 25 25 ns min CH Clock Width Low t 25 25 ns min CL Load Pulsewidth t 25 25 ns min LD LSB CLK to LD DAC t 00 ns min ASB 1, 2 AC CHARACTERISTICS Output Current Settling Time t To 0.01% of Full Scale, Ext Op Amp OP42 1 1 s max S DAC Glitch Q Data = 000 to FFF to 000 , V = 0 V 20 20 nVs max H H H REF Feedthrough (V /V)FT V = 20 V p-p, Data = 000 , f = 10 kHz 1 1 mV p-p OUT REF REF H Total Harmonic Distortion THD V = 6 V rms, Data = FFF , f = 1 kHz 85 85 dB typ REF H 5 Output Noise Density e 10 Hz to 100 kHz Between R and I 17 17 nV/Hz max n FB OUT Multiplying Bandwidth BW 3 dB, V /V , V = 100 mV rms, Data = FFF 2.4 2.4 MHz typ OUT REF REF H SUPPLY CHARACTERISTICS Power Supply Range V 4.5/5.5 4.5/5.5 V min/max DD RANGE Positive Supply Current I V = 0 V or V 10 10 A max DD LOGIC DD Power Dissipation P V = 0 V or V 50 50 W max DISS LOGIC DD Power Supply Sensitivity PSS V = 5% 0.002 0.002 %/% max DD NOTES 1 Using internal feedback resistor R , see Figure 19 test circuit with V = 10 V. FB REF 2 These parameters are guaranteed by design and not subject to production testing. 3 Calculated from worst case R : I (LSB) = (R I 4096)/V . REF ZSE REF LKG REF 4 All input control signals are specified with t = t = 2 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. R F 5 Calculation from e = 4KTRB where: K = Boltzmann Constant (J/K), R = Resistance ( ), T = Resistor Temperature (K), B = 1 Hz Bandwidth. n Specifications subject to change without notice. REV. B 2