Dual 12-Bit Double-Buffered a Multiplying CMOS D/A Converter DAC8222 FUNCTIONAL DIAGRAM FEATURES Two Matched 12-Bit DACs on One Chip Direct Parallel Load of All 12 Bits for High Data Throughput Double-Buffered Digital Inputs 12-Bit Endpoint Linearity ( 1/2 LSB) Over Temperature +5 V to +15 V Single Supply Operation DACs Matched to 1% Max Four-Quadrant Multiplication Improved ESD Resistance Packaged in a Narrow 0.3 24-Lead DIP and 0.3 24- Lead SOL Package Available in Die Form APPLICATIONS Automatic Test Equipment Robotics/Process Control/Automation Digital Gain/Attenuation Control Ideal for Battery-Operated Equipment GENERAL DESCRIPTION double-buffered digital inputs will allow both DACs to be The DAC8222 is a dual 12-bit, double-buffered, CMOS digital- simultaneously updated. to-analog converter. It has a 12-bit wide data port that allows a DAC8222s monolithic construction offers excellent DAC-to- 12-bit word to be loaded directly. This achieves faster through- DAC matching and tracking over the full operating tempera- put time in stand-alone systems or when interfacing to a 16-bit ture range. The chip consists of two thin-film R-2R resistor processor. A common 12-bit input TTL/CMOS compatible ladder networks, four 12-bit registers, and DAC control logic data port is used to load the 12-bit word into either of the two circuitry. The device has separate reference-input and feedback DACs. This port, whose data loading is similar to that of a RAMs resistors for each DAC and operates on a single supply from write cycle, interfaces directly with most 12-bit and 16-bit bus +5 V to +15 V. Maximum power dissipation at +5 V using systems. (See DAC8248 for a complete 8-bit data bus interface zero or V logic levels is less than 0.5 mW. DD product.) A common bus allows the DAC8222 to be packaged The DAC8222 is manufactured with highly stable thin-film re- in a narrow 24-lead 0.3 DIP and save PCB space. sistors on an advanced oxide-isolated, silicon-gate, CMOS The DAC is controlled with two signals, WR and LDAC. With technology. Improved latch-up resistant design eliminates the logic low at these inputs, the DAC registers become transparent. need for external protective Schottky diodes. This allows direct unbuffered data to flow directly to either DAC output selected by DAC A/DAC B. Also, the DACs REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: DAC8222SPECIFICATIONS ELECTRICAL CHARACTERISTICS ( V = +5 V or +15 V, V = V = +10 V, V = V = 0 V AGND = DGND = 0 V DD REF A REF B OUT A OUT B T = Full Temperature Range Specified in Absolute Maximum Ratings unless otherwise noted. Specifications apply for DAC A and DAC B.) A Parameter Symbol Conditions Min Typ Max Units STATIC ACCURACY Resolution N 12 Bits Relative Accuracy INL Endpoint Linearity Error DAC8222A/E/G 1/2 LSB DAC8222F/H 1 LSB Differential Nonlinearity DNL All Grades are Guaranteed Monotonic 1 LSB 1 Full-Scale Gain Error G DAC8222A/E 1 LSB FSE DAC8222G 2 LSB DAC8222F/H 4 LSB Gain Temperature Coefficient Gain/ Temperature TCG (Notes 2, 7) 2 5 ppm/C FS Output Leakage Current I (Pin 2), I All Digital Inputs = T = +25C 5 10 nA OUT A LKG A I (Pin 24) 0000 0000 0000 T = Full Temp. Range 50 nA OUT B A Input Resistance (V , V)R (Note 9) 8 11 15 k REF A REF B REF R 0.2 1% REF Input Resistance Match R REF DIGITAL INPUTS Digital Input High V V = +5 V 2.4 V INH DD V = +15 V 13.5 V DD Digital Input Low V V = +5 V 0.8 V INL DD = +15 V 1.5 V V DD Input Current I V = 0 V or V T = +25C 0.001 1 A IN IN DD A and V or V T = Full Temp. Range 10 A INL INH A 2 Input Capacitance C DB0DB11 10 pF IN WR, LDAC, DAC A/DAC B 15 pF POWER SUPPLY Supply Current I All Digital Inputs V or V 2mA DD INL INH All Digital Inputs 0 V or V 10 100 A DD DC Power Supply Rejection Ratio PSRR V = 5% 0.002 %/% DD ( Gain/ V ) DD 2 AC PERFORMANCE CHARACTERISTICS 4, 5 Propagation Delay t T = +25C 350 ns PD A 5, 6 Current Settling Time t T = +25C1 s S A Output Capacitance C Digital Inputs = All 0s 90 pF O C , C 90 pF OUT A OUT B Digital Inputs = All 1s 120 pF C , C 120 pF OUT A OUT B AC Feedthrough at FT V to I V = 20 V p-p 70 dB A REF A OUT A REF A I or I f = 100 kHz T = +25C 70 dB OUT A OUT B A V to I V = 20 V p-p 70 dB REF B OUT B REF B FT f = 100 kHz T = +25C 70 dB B A 2, 3 SWITCHING CHARACTERISTICS V = +5 V V = +15 V DD DD 8 10 55C to +125C All Temps +25C40C to +85C DAC Select to t 150 180 210 60 ns min AS Write Set-Up Time DAC Select to t 0 0 0 0 ns min AH Write Hold Time LDAC to t 80 100 120 60 ns min LS Write Set-Up Time LDAC to t 20 20 20 20 ns min LH Write Hold Time Data Valid to t 220 240 260 100 ns min DS Write Set-Up Time Data Valid to t 00 0 10 ns min DH Write Hold Time Write Pulse Width t 130 160 170 90 ns min WR LDAC Pulse Width t 100 120 130 60 ns min LWD 16 NOTES Settling time is measured from 50% of the digital input change to where the 11 Measured using internal R and R . Both DAC digital inputs = 1111 1111 1111. output voltage settles within 1/2 LSB of full scale. FB A FB B 12 17 Guaranteed and not tested. Gain TC is measured from +25C to T or from +25C to T . MIN MAX 13 18 See timing diagram. These limits apply for the commercial and industrial grade products. 14 19 From 50% of digital input to 90% of final analog output current. Absolute temperature coefficient is approximately +50 ppm/C. 10 V = V = +10 V OUT A, OUT B load = 100 , C = 13 pF. These limits also apply as typical values for V = +12 V with +5 V CMOS REF A REF B EXT DD 15 WR, LDAC = 0 V DB0DB11 = 0 V to V or V to 0 V. logic levels and T = +25C. DD DD A Specifications subject to change without notice. 2 REV. C