Quad 12-Bit Serial Voltage Output DAC Data Sheet DAC8420 FEATURES FUNCTIONAL BLOCK DIAGRAM VREFHI VDD Guaranteed monotonic over temperature 5 1 Excellent matching between DACs DAC8420 10 SDI Unipolar or bipolar operation REG DAC A 7 VOUTA A Buffered voltage outputs 12 High speed serial digital interface Reset-to-zero scale or midscale 12 CS CLK 11 REG Wide supply range, +5 V only to 15 V SHIFT DAC B 6 VOUTB B REGISTER Low power consumption (35 mW maximum) Available in 16-Lead PDIP, SOIC, and CERDIP packages NC 13 REG APPLICATIONS DAC C 3 VOUTC 4 C Software controlled calibration Servo controls 14 DECODE LD Process control and automation REG DAC D 2 VOUTD D 2 ATE 9 16 15 4 8 GND CLSEL CLR VREFLO VSS Figure 1. GENERAL DESCRIPTION The DAC8420 is a quad, 12-bit voltage-output DAC with serial The user-programmable reset control CLR forces all four DAC digital interface in a 16-lead package. Utilizing BiCMOS tech- outputs to either zero scale or midscale, asynchronously overriding nology, this monolithic device features unusually high circuit the current DAC register values. The output voltage range, density and low power consumption. The simple, easy-to-use determined by the inputs VREFHI and VREFLO, is set by the serial digital input and fully buffered analog voltage outputs user for positive or negative unipolar or bipolar signal swings require no external components to achieve a specified per- within the supplies, allowing considerable design flexibility. formance. The DAC8420 is available in 16-lead PDIP, SOIC, and CERDIP The 3-wire serial digital input is easily interfaced to micro- packages. Operation is specified with supplies ranging from +5 V processors running at 10 MHz with minimal additional only to 15 V, with references of +2.5 V to 10 V, respectively. circuitry. Each DAC is addressed individually by a 16-bit serial Power dissipation when operating from 15 V supplies is less than word consisting of a 12-bit data word and an address header. 255 mW (maximum) and only 35 mW (maximum) with a +5 V supply. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20032016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 00275-001DAC8420 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Correct Operation of CS and CLK........................................... 13 Applications ....................................................................................... 1 Using CLR and CLSEL............................................................... 13 Functional Block Diagram .............................................................. 1 Programming the Analog Outputs .......................................... 13 General Description ......................................................................... 1 VREFHI Input Requirements ................................................... 15 Revision History ............................................................................... 2 Power-Up Sequence ................................................................... 15 Specifications ..................................................................................... 3 Applications ..................................................................................... 16 Electrical Characteristics ............................................................. 3 Power Supply Bypassing and Grounding ................................ 16 Absolute Maximum Ratings ............................................................ 6 Analog Outputs .......................................................................... 16 Thermal Resistance ...................................................................... 6 Reference Configuration ........................................................... 17 ESD Caution .................................................................................. 6 Isolated Digital Interface ........................................................... 18 Pin Configurations and Function Descriptions ........................... 8 Dual Window Comparator ....................................................... 19 Typical Performance Characteristics ............................................. 9 MC68HC11 Microcontroller Interfacing ................................ 19 Theory of Operation ...................................................................... 13 DAC8420 to M68HC11 Interface Assembly Program .......... 20 Introduction ................................................................................ 13 Outline Dimensions ....................................................................... 21 Digital Interface Operation ....................................................... 13 Ordering Guide .......................................................................... 22 REVISION HISTORY 9/2016Rev. B to Rev. C Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 22 5/2007Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Endnote 3 ...................................................................... 4 Changes to Table 3 ............................................................................ 6 Changes to Table 4 ............................................................................ 2 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 23 9/2003Rev. 0 to Rev. A Changes to General Description .................................................... 1 Deleted Wafer Test Limits table ...................................................... 4 Deleted Dice Characteristics ........................................................... 4 Updated Ordering Guide ................................................................. 4 Added Power-Up Sequence section ............................................. 12 Updated Outline Dimensions ....................................................... 17 Rev. C Page 2 of 23