DEMO CIRCUIT 1054A/B LTC4242 QUICK START GUIDE LTC4242 Dual Port, PCI Express Hot Swap Controller DESCRIPTION L, LTC, LTM, LT, Burst Mode, OPTI-LOOP, Over-The-Top and Demonstration Circuit 1054A PolyPhase are registered trademarks of Linear Technology Cor- poration. Adaptive Power, C-Load, DirectSense, Easy Drive, showcases the LTC4242 Dual Slot Hot FilterCAD, Hot Swap, LinearView, Module, Micropower Swap Controller for PCI Express. SwitcherCAD, Multimode Dimming, No Latency , No Latency Delta-Sigma, No R , Operational Filter, PanelProtect, Power- SENSE DC1054A features two PCI-X slots Path, PowerSOT, SmartStart, SoftSpan, Stage Shedding, into which DC1054B may be inserted. SwitcherCAD, ThinSOT, UltraFast and VLDO are trademarks of Linear Technology Corporation. Other product names may be Two DC1054B daughter cards are trademarks of the companies that manufacture the products. included with each DC1054A. LEDs indicate the presence of input and output voltages, as well as faults andpower goo conditions. The daughter cards are loaded with the maximum capacitance on each supply. Design files for this circuit board are available. Call the LTC fac- tory. LTC is a trademark of Linear Technology Corporation PERFORMANCE SUMMARY Specifications are at TA = 25C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Supply Range 2.7 3.3 6.0 V CC +12VIN Input Supply Range 10.1 12 14.4 V +3.3VIN Input Supply Range 3.0 3.3 6.0 V 3.3VAUX Input Supply Range 3.0 3.3 6.0 V INPUT I Load Current 5.5 A 12VOUT I Load Current 3 A 3.3VOUT I Load Current 375 mA 3.3VAUXOUT OPERATING PRINCIPLES Board Layout Supply inputs and logic control inputs are located along the left The Vcc pin bypass capacitor is side of DC1054B. Along the right located on the bottom of the side are the supply outputs and board, directly under the LTC4242 fault and power good outputs. where it can be of greatest effi- LEDs are located adjacent to in- cacy. puts and outputs of interest. 1 L TC4242 Input Bypassing In a practical application, the Z2 and Z3) have been included near input supplies are bypassed near the input turrets to protect the supply switches (MOSFETs Q1- against these transients. Surges Q4). For the purposes of DC1054A, may also arise as a result of poor bypassing has been omitted except loop response in a bench supply. for the Vcc bypass capacitor C1, located directly under the Second, dips in the input voltage LTC4242. This simplification af- arising from load steps and wiring fects the operation of the board resistance and inductance may ac- in two ways. First, inductive re- tivate undervoltage lockout and action on the inputs arising from temporarily shut down the LTC4242, bench test leads during overload particularly if both slots are or short circuit tests can cause fully loaded. Take care to ensure potentially damaging high voltage that the proper supply voltage is surges or transients to appear at delivered to the board, particu- the input pins of the LTC4242. larly at the +3.3VIN input. Transient voltage suppressors (Z1, Input Supplies There are three supply inputs 3.3VAUX 1A along the left side of DC 1054A, +3.3VIN 7A with adjacent LEDs to indicate +12VIN 12A when power is applied. In the lower left are turrets for the Vcc for the LTC4242 may be ob- main supply inputs, +12VIN and tained from either the 3.3VAUX +3.3VIN. In the upper left is a supply or from the +3.3VIN supply turret for connecting the 3.3VAUX by setting jumper JP9. A separate input. power supply for 3.3VAUX is not strictly necessary 3.3VAUX and 1A supplies are adequate to power +3.3VIN may be powered from the the board, but to deliver full same source as long as adequate power to both ports the following current is available to power the ratings are recommended: combined load. Controlling the LTC4242 There are several ways to control Port 1 is activated by pulling low the LTC4242. Each port is fully the enable pin, EN1 . Jumper JP7 independent and identical to the provides 4 options for controlling other, so this discussion will de- EN . It can be forced HIGH or LOW, scribe the operation of port 1. connected to an external logic Note that external logic signals signal (EXT), or operated by the are applied via the turrets adja- short pins on the daughter card cent to each jumper. using the J1(A1) jumper position. For normal operation, JP7 should 2