DC1220B DC1220B QUICK START GUIDE QUICK START GUIDE LTC3225EDDB Low Profile Regulated Dual Cell SuperCAP Charger DESCRIPTION Demonstration circuit DC1220B is a Low Profile Regu- to survive a continuous short-circuit from PROG to GND. lated Dual Cell SuperCAP Charger featuring the LTC3225. When the input supply is removed, the LTC3225 auto- The LTC3225 is a constant-current SuperCAP charger matically enters a low current state, drawing less than designed to charge two SuperCAPs in series to a fixed 1A from the SuperCAPs. output voltage of 4.8V/5.3V from a 2.9V to 5.5V input The LTC3225 is offered in a 10-lead (3mm 2mm) DFN supply. Automatic cell balancing is achieved during the package. charging phase. Design files for this circuit board are available. Call Low input noise, low quiescent current and low external the LTC factory. parts count make the LTC3225 ideally suited for small, L, LTC, LTM, LT, Burst Mode, are registered trademarks of Linear Technology Corporation. battery-powered applications. Charging current level is All other trademarks are the property of their respective owners. programmed through an external resistor. Internal cur- rent limit and thermal shutdown circuitry allows the part TABLE 1. TYPICAL SPECIFICATIONS (25C) 2.9V to 5.5V Input Voltage Range: V CC Charge Current 30mA or 150mA dependant on JP3 setting VOUT 4.8V or 5.3V dependant on JP2 setting OPERATING PRINCIPLES The LTC3225 is a dual cell SuperCAP charger using a constant-current/constant-voltage algorithm. Its ability to control input charge currents up to 300mA and achieve automatic cell balancing during charg- ing makes it well suited for charging two series connected SuperCAPs. The LTC3225 includes an internal switched capacitor charge pump to boost Vin to a regulated output voltage. A unique architec- ture maintains relatively constant input current for the lowest possible input noise. The basic charger circuit requires only three external components. 1 DC1220B QUICK START GUIDE QUICK START PROCEDURE Using short twisted pair leads for any power connec- 12. Turn on Load1 and set to 200mA. Monitor PGOOD tions and with all loads and power supplies off, refer and VOUT. When PGOOD goes low, verify that to Figure 1 for the proper measurement and equip- VOUT is ~4.9V. ment setup. 13. Set JP1 to SHDN, increase Load1 to 500mA and 1. Jumper and Load Settings to start: allow the SuperCAP to discharge to 1.5V at which JP1 (RUN) = SHDN point Load1 will be set to 0mA and turned off. JP2 (VOUT SELECT) = 5.3V 14. Set JP2 to 4.8V JP3 (Iin LIMIT) = 30mA LOAD1 = off 15. Set JP1 to the RUN position. Verify that the input current is ~300mA. Verify that PGOOD is low. 2. Set VIN to 3.0V and verify that the input current is less than 10mA. Verify that VOUT is less than 16. Monitor PGOOD and VOUT. When PGOOD goes 3.8V indicating that the SuperCAP is in a low high, verify that VOUT is ~4.55V. charge state. 17. Verify that VOUT is ~4.8V when the input current 3. Set JP1 to the RUN position. Verify that the input drops to less than 10mA indicating a fully charged current is ~60mA. Verify that VOUT is less than capacitor. 4.0V and that PGOOD is low. 18. Turn on Load1 and set to 200mA. Monitor PGOOD 4. Monitor PGOOD and VOUT. When PGOOD goes and VOUT. When PGOOD goes low, verify that high, verify that VOUT is ~5.0V. VOUT is ~4.45V. 5. Verify that VOUT is ~5.3V when the input current 19. Set JP1 to SHDN, increase Load1 to 500mA and drops to less than 10mA indicating a fully charged allow the SuperCAP to discharge to 1.0V at which capacitor. point Load1 will be set to 0mA and turned off. 6. Turn on Load1 and set to 50mA. Monitor PGOOD and VOUT. When PGOOD goes low, verify that APPLICATION INFORMATION VOUT is ~4.9V. 7. Set JP1 to SHDN and allow the SuperCAP to dis- This demo circuit is designed to demonstrate the full charge to 1.5V at which point Load1 will be set to capability of the LTC3225 Low Profile Regulated Dual 0mA and turned off. Cell SuperCAP Charger. Not all components are re- 8. Set JP3 to 150mA quired in all applications. The critical circuit compo- nents are on the top of the board near the IC and 9. Set JP1 to the RUN position. Verify that the input listed in the Required Circuit Components section of current is ~300mA. Verify that PGOOD is low. the Bill of Materials, see Figure 4. 10. Monitor PGOOD and VOUT. When PGOOD goes high, verify that VOUT is ~5.0V. The style and value of the input capacitors C2 and C6 controls the amount of ripple present at the input pin 11. Verify that VOUT is ~5.3V when the input current drops to less than 10mA indicating a fully charged (Vin). To reduce noise and ripple, it is recommended capacitor. that a low equivalent series resistance (ESR) multi- layer ceramic chip capacitor (MLCCs) be used. A 10nH inductor between C6 and C2 will reject fast cur- 2