QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1255 16-BIT, 250KSPS ADC LTC1605CG/LTC1606CG DESCRIPTION The LTC1606 is a 250Ksps ADC that draws only Demonstration circuit 1255 provides the user a 75mW from a single +5V Supply, while the LTC1605 means of evaluating the performance of the is a 100Ksps ADC that draws only 55mW from a sin- LTC1605/LTC1606 and is intended to demonstrate gle +5V supply. DC1255 can use either part. The fol- recommended grounding, part placement, routing lowing text refers to the LTC1606 but it also applies and bypassing. to the LTC1605 with appropriate sampling frequency Design files for this circuit board are available. Call the LTC factory. considerations. LTC is a trademark of Linear Technology Corporation Figure1. Connection Diagram 1 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1255 16-BIT, 250KSPS ADC DC718B QUICK START PROCEDURE Connect DC1255A to a DC718B USB High Speed Data Complete software documentation is available from the Collection Board using connector J2. Connect DC718B Help menu. Updates can be downloaded from the Tools to a host PC with a standard USB A/B cable. Apply 7V- menu. Check for updates periodically as new features 9V DC to the 7V-9V and GND terminals. Apply +15V may be added. and -15V to the indicated terminals, if the internal The Pscope software should recognize DC1255A and buffer is to be used (default). Apply a low jitter signal configure itself automatically. source to J1. As a clock source, either the onboard Click the Collect button (See Figure 2) to begin acquiring clock or a low jitter 250kHz 10dBm sine wave or data. Depending on which board was previously used by square wave to connector J3 can be used. Note that J3 Pscope, it may be necessary to press Collect a second has a 50 termination resistor to ground. Run the time. The Collect button then changes to Pause, which QuickEval-II software (Pscope.exe version K51 or later) can be clicked to stop data acquisition. supplied with DC718B or download it from www.linear.com. DC1255 SETUP the form of an inverter (U14) followed by a 200nsec DDCC PPoowweerr DDCC PPoowweerr delay, feeding, along with the original clock source, a DC1255 requires 7-9VDC at approximately 24mA and two input NAND gate (U7B). This will generate an ap- +/- 15V to power amplifier U3. If you do not use U3 proximate 200nsec active low pulse at the ADC if the (see jumper JP1) you do not have to provide +/-15V. The 7-9VDC clock high time is greater than 200nsec. A 50% duty supply powers the ADC through a LT1761-5 regulator cycle clock at 250kHz is typically used to test these witch provides protection against accidental reverse demo boards. Shorter duty cycle pulses (active High bias. See Figure 1 for connection details. at J3) can be used to a minimum of 40nsec. Clock Source DDDDaaaattttaaaa OOOOuuuuttttppppuuuutttt JP10 (CLK) determines whether DC1255 is inter- Parallel data output from this board (0V-3.3V), if not nally (default) or externally clocked. The internal connected to DC718, can be acquired by a logic ana- clock consists of an ECS 1MHz clock oscillator, lyzer, and subsequently imported into a spreadsheet, which is divided by a 74VHC161 counter. This oscil- or mathematical package depending on what form of lator can be turned off by setting JP9 (OSCEN) to digital signal processing is desired. the OFF position. Jumpers (JP4-JP7) set the inter- nal clock divider ratio for the appropriate ADC BBBBYYYYTTTTEEEE aaaannnndddd CCCCSSSS JJJJuuuummmmppppeeeerrrrssss (LTC1605 or LTC1606). See the table in Figure 1 The demo board is typically shipped with BYTE (JP3) for jumper settings. and CS (JP8) tied to ground. If you intend to operate For an external clock, you must provide a low jitter this device in a fashion that involves these lines, you 10dBm sine or square wave to J3. Note that J3 has a can use the jumpers as a means of introducing these 50 termination resistor to ground. Driving this input signals from an external source. with logic will be difficult. Slow rising edges may compromise SNR of the converter in the presence of RReeffeerreennccee RReeffeerreennccee high-amplitude higher frequency input signals. The JP2 allows you to select an on chip reference or an demo board incorporates an edge detector circuit in external LT1019A-2.5 (default) as the reference. The 2