QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1335A-A HIGH POWER, HIGH EFFICIENCY POE PD INTERFACE WITH INTEGRATED SWITCHING REGULATOR LTC4269IDKD-1 DESCRIPTION Demonstration circuit 1335A-A is a high-power sup- trols a high-power, small-sized power supply that ply featuring the LTC4269IDKD-1. This board acts utilizes a highly-efficient isolated flyback topology as an IEEE 802.3at compliant, high power Power- with synchronous rectification. The DC1335A-A sup- over-Ethernet (PoE), Powered Device (PD) and con- plies a 3.3V output at up to 7A. nects at the RJ45 to a compatible high power Power DC1335A-A also demonstrates the use of an auxiliary Sourcing Equipment (PSE) device, such as the 48V wall adapter. When present, the auxiliary supply DC1366. becomes the dominant supply over PoE to provide The LTC4269IDKD-1 provides IEEE802.3at standard power. (PoE+) PD interfacing and power supply control. Design files for this circuit board are available. When the PD is fully powered, the PD interface Call the LTC factory. switches power over from the PSE to the switcher through an internal, low resistance, high power , LTC and LT are registered trademarks of Linear Technology Corporation. MOSFET. The highly integrated LTC4269IDKD-1 con- Table 1. Performance Summary (T = 25C) A PARAMETER CONDITION VALUE Port Voltage (V ) At Ethernet port 37V 57V PORT Auxiliary Voltage (V ) From Aux- to Aux+ terminals 44V 57V AUX Output Voltage (V ) Initial Set-point V = 37V to 57V, I = 0A to 5A 3.33V 1% OUT PORT OUT Maximum Output Current V = 42V 6.6A PORT Typical Output Voltage Ripple V = 50V, I = 6.6A 40mV (typ) IN OUT PP Output Regulation Over Entire Input Voltage and Output Current Range 0.5% (typ) Peak to Peak Deviation with Load Step of 2.5A to 5A 450mV (typ) Load Transient Response Settling Time (within 1% of V ) < 100us (typ) OUT Switching Frequency 250kHz (typ) Efficiency V = 50V, I = 6.5A, not incl. diode bridge 89% (typ) PORT OUT OPERATING PRINCIPLES A compatible high power PSE board, such as the used at the input to improve efficiency over standard DC1366, is connected to the DC1335A-A at the RJ45 diode bridges. The LTC4269IDKD-1 provides an connector J1 (see the schematic). As required by IEEE802.3at standard PoE 25k signature resistance IEEE802.3at, a diode bridge is used across the data and is set for a power class 4. When the PD is pow- pairs and signal pairs. Schottky diodes (D2-9) are ered and voltage is above the PoE On Voltage, the 1 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1335A-A HIGH POWER, HIGH EFFICIENCY POE PD INTERFACE WITH INTEGRATED SWITCHING REGULATOR LTC4269IDKD-1 switches the port voltage over to the drive (PG) and Synchronous Gate (SG) drive is then Pulse Width Modulated (PWM) in order to keep the power supply controller through its internal MOSFET output voltage constant. The synchronous gate drive which lies between the V and V pins. This volt- PORTN NEG signal is transmitted to the secondary via the small age charges C18/19 through a trickle charge resistor, signal transformer, T2. The output of T2 then drives R9 to power the bias pin, V , of the power supply CC a discrete gate drive buffer, R22 and Q6/7 in order to controller. Once the bias power gets to its V CC(ON) achieve fast gate transition times, hence a higher effi- threshold, the IC begins a controlled soft-start of the ciency. output. As the output voltage rises, bias power is taken over by the bias supply made up of T1s bias The two-stage input filter, C5, L2, and C6 and output winding and D11. filter, C1/3, L1, and C10 are the reasons that this PoE flyback supply has exceptionally low differential mode When the soft-start period is over, the output voltage conducted emissions. is regulated by observing the pulses across the bias winding during the flyback time. The Primary Gate QUICK START PROCEDURE Demonstration circuit 1335A-A is easy to set up to a. Connect a PoE+ capable PSE with a CAT-5 cable evaluate the performance of the LTC4269IDKD-1 in a to the RJ45 connector, J1. See Figure 1. PoE+ PD application. Refer to Figure 1 for proper b. Or, connect a 37V to 57V capable power supply equipment setup and follow the procedure below: (Power Supply in Figure 1) across VPORT P and VPORT N. NOTE: When measuring the input or output voltage c. If evaluating the auxiliary power supply (Auxil- ripple, care must be taken to avoid a long ground lead iary Supply in Figure 1) capability, connect a 44V on the oscilloscope probe. Measure the output (or to 57V capable power supply across AUX+ to AUX-. input) voltage ripple by touching the probe tip and probe ground directly across the +VOUT and VOUT 3. Check for the proper output voltage of 3.33V. (or VPORT P and VPORT N) terminals. See Figure 2 4. Once the proper output voltage is confirmed, adjust for proper scope probe technique. the load within the operating range and observe the 1. Place test equipment (voltmeter, ammeter, and output voltage regulation, ripple voltage, efficiency electronic load) across output. and other parameters. 2. Input supplies: 2