QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1339 LOW NOISE, 500KSPS, 12-BIT ADC LTC2302 DESCRIPTION Demonstration circuit 1339 features the DC890B if precise sampling rates are required LTC2302 low noise, 500ksps, 12-Bit, ADC. or to demonstrate AC performance such as The LTC2302 has an SPI compatible serial SNR, THD, SINAD and SFDR. Alternatively, interface that can be used to select channel by connecting the DC1339A into a customer polarity and unipolar or bipolar settings. application, the performance of the LTC2302 DC1339A demonstrates the DC and AC can be evaluated directly in that circuit. performance of the LTC2302 in conjunction with the DC590B QuikEval and DC890B Fast Design files for this circuit board are DAACS data collection boards. Use DC590B available. Call the LTC factory. LTC is a trademark of Linear Technology Corporation to demonstrate DC performance such as peak-to-peak noise and DC linearity. Use Figure 1. DC1339A Connection Diagram 1 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1339 LOW NOISE, 500KSPS, 12-BIT ADC DC890B QUICK START PROCEDURE Connect DC1339A to a DC890B USB High has a 50 termination resistor to ground, Speed Data Collection Board using connector which will prevent most logic from driving this J2. Connect DC890B to a host PC with a pin directly. Run the Fast DAACS software standard USB A/B cable. Apply 6V-9V DC to (Pscope.exe version K51 or later) supplied with the 6V-9V and GND terminals. Apply a low DC890B or download it from www.linear.com. jitter signal source to IN+ on connector J1. Complete software documentation is available Apply a low jitter clock with a maximum from the Help menu. Updates can be frequency of 40MHz to connector J3. The clock downloaded from the Tools menu. Check for can be a sine wave or square wave with updates periodically as new features may be maximum amplitude of 14dBm. Note that J3 added. PSCOPE SOFTWARE CONFIGURATION The Pscope software will recognize DC1339A Check Bipolar if the JP5 UNI jumper is set to and configure itself automatically. The default GND. An example of the ADC configuration configuration is for IN+ with respect to IN- in menu is shown in Figure 3. JP3 should be unipolar mode. Make sure that the jumpers are changed from GND to VREF/2 in bipolar set as shown in Figure 2. If bipolar mode is mode, so that the minus input is biased desired, it will be necessary to change the halfway between ground and Vref. Pscope ADC configuration setting as well as Click the Collect button (See Figure 4) to jumpers JP3 and JP5. From the front page of begin acquiring data. Depending on which the software select ADC Configuration from board was previously used by Pscope it may the Configure menu. Select 12-Bits, be necessary to press Collect a second time. Alignment 12, FPGA Ld Serial 2308 Class, 1- The Collect button then changes to Pause, Channel. Do not check Positive Edge Clk. which can be used to pause data acquisition. Figure 2. Jumper Settings Figure 3. User Configure Menu 2