DEMO MANUAL DC1525A
LTC2175-14/-12,
LTC2174-14/-12, LTC2173-14/-12, LTC2172-14/-12,
LTC2171-14/-12, LTC2170-14/-12
12-Bit/14-Bit, 25Msps to 125Msps Quad ADCs
DESCRIPTION
Demonstration circuit 1525A supports a family of the DC1525A is supplied with the appropriate ADC. The
14-Bit/12-Bit 25Msps to 125Msps ADCs. Each assem- circuitry on the analog inputs is optimized for analog input
bly features one of the following devices: LTC 2175-14, frequencies from 5MHz to 140MHz. Refer to the data sheet
LTC2175-12, LTC2174-14, LTC2174-12, LTC2173-14, for proper input networks for different input frequencies.
LTC2173-12, LTC2172-14, LTC2172-12, LTC2171-14,
Design files for this circuit board are available at
LTC2171-12, LTC2170-14, LTC2170-12 high speed,
DEMO MANUAL DC1525A
PERFORMANCE SUMMARY (T = 25C)
A
PARAMETER CONDITION VALUE
Supply Voltage: DC1525A Depending on Sampling Rate and the A/D Converter Provided, Optimized for 3V
this Supply Must Provide Up to 500mA. [3V 6.0V Min/Max]
Analog Input Range Depending on SENSE Pin Voltage 1V to 2V
P-P P-P
Logic Input Voltages Minimum Logic High 1.3V
Maximum Logic Low 0.6V
Logic Output Voltages (Differential) Nominal Logic Levels (100 Load, 3.5mA Mode) 350mV/1.25V Common Mode
Minimum Logic Levels (100 Load, 3.5mA Mode) 247mV/1.25V Common Mode
Sampling Frequency (Convert Clock Frequency) See Table 1
Encode Clock Level Single-ended Encode Mode (ENC Tied to GND) 0V to 3.6V
Encode Clock Level Differential Encode Mode (ENC Not Tied to GND) 0.2V to 3.6V
Resolution See Table 1
Input Frequency Range See Table 1
SFDR See Applicable Data Sheet
SNR See Applicable Data Sheet
QUICK START PROCEDURE
Demonstration circuit 1525A is easy to set up to evaluate J14: LANE: Selects either 1 lane or 2 lane output modes
the performance of the LTC2175 A/D converters. Refer to (Default Removed) NOTE: The DC1371 does not support
Figure 1 for proper measurement equipment setup and 1 lane operation.
follow this procedure.
J15: SHDN: Enables and disables the LTC2175. (De-
faultRemoved)
Setup
J2: WP: Enable/Disables write protect for the EEPROM.
If a DC1371 QuikEval II Data Acquisition and Collection
(Default Removed)
System was supplied with the DC1525A demonstration
circuit, follow the DC1371 Quick Start Guide to install the Note: optional jumper should be left open to ensure proper
required software and for connecting the DC1371 to the serial configuration.
DC1525A and to a PC.
Applying Power and Signals to the DC1525A
DC1525A Demonstration Circuit Board Jumpers Demonstration Circuit
The DC1525A demonstration circuit board should have The DC1371 is used to acquire data from the DC1525A,
the following jumper settings as default positions: (as the DC1371 must FIRST be connected to a powered USB
per Figure 1). port and have equal to 5V applied power BEFORE applying
+
3.6V to 6V across the pins marked V and GND on the
J13: PAR/SER: Selects Parallel or Serial programming
DC1525A. DC1525A requires 3.6V for proper operation.
mode. (Default Serial)
Regulators on the board produce the voltages required for
Optional Jumpers:
the ADC. The DC1525A demonstration circuit requires up
J8: Term: Enables/Disable optional output termination.
to 500mA depending on the sampling rate and the A/D
(Default Removed)
converter supplied.
J5: ILVDS: Selects either 1.75mA or 3.5mA of output
The DC1525A should not be removed, or connected to
current for the LVDS drivers. (Default Removed)
the DC1371 while power is applied.
dc1525af
2