DEMO MANUAL DC1571A LTC2383-16/LTC2382-16/ LTC2381-16: 16-Bit, 1.0Msps/ 0.5Msps/0.25Msps Low Power, Low Noise ADCs DESCRIPTION performance such as peak-to-peak noise and DC linear- The LTC 2383-16/LTC2382-16/LTC2381-16 are low power, ity. Use the DC718 if precise sampling rates are required low noise ADCs with serial outputs that can operate from a or to demonstrate AC performance such as SNR, THD, single 2.5V supply. The following text refers to the LTC2383- SINAD and SFDR. The demonstration circuit DC1571A is 16 but applies to all three parts. The only difference being intended to demonstrate recommended grounding, com- the maximum sample rates. The LTC2383-16 supports a ponent placement and selection, routing and bypassing for 2.5V fully differential input range with a 92dB SNR, con- this ADC. Several suggested driver circuits for the analog sumes only 13mW and achieves 2LSB INL max with no inputs will also be presented. missing codes at 16-bits. The DC1571A demonstrates the DC and AC performance of the LTC2383-16 in conjunction Design les for this circuit board are available at with the DC590 QuickEval and DC718 Fast DAACS data DEMO MANUAL DC1571A DC718 QUICK START PROCEDURE Check to make sure that all switches and jumpers are Run the QuickEval-II software (Pscope.exe version K68 set as shown in the connection diagram of Figure 1. The or later) supplied with the DC718 or download it from default connections con gure the ADC to use the onboard www.linear.com. reference and common mode voltages. The analog input Complete software documentation is available from the is AC coupled. Connect the DC1571A to a DC718 USB Help menu. Updates can be downloaded from the Tools High Speed Data Collection Board using connector J2. menu. Check for updates periodically as new features Connect the DC718 to a host PC with a standard USB A/B may be added. cable. Apply 9V to the indicated terminals. Apply a low The Pscope software should recognize the DC1571A and jitter signal source to J4. The default setup uses a single con gure itself automatically. ended to differential converter so that it is only necessary to apply an input signal to J4. Connect a low jitter 80MHz Click the Collect button (See Figure 6) to begin acquiring 3.3Vpp sine wave or square wave to connector J1. Note data. The Collect button then changes to Pause, which that J1 has a 50 termination resistor to ground. can be clicked to stop data acquisition. DC590 SETUP To use the DC590 with the DC1571A it is necessary to to a DC590 USB serial controller using the supplied 14- apply 9V and ground to the 9V and GND terminals or conductor ribbon cable. Apply a signal source to J4 or J4 disable ampli er U15 by moving R32 and R36 to R31 and and J8 depending on how the DC1571A is con gured. R38 respectively. If U15 is disabled, it is required that J4 Run the evaluation software supplied with the DC590 or and J8 are both driven. If U15 is not disabled then it is download it from www.linear.com. The correct control only necessary to drive J4. Connect the DC590 to a host panel will be loaded automatically. Click the COLLECT PC with a standard USB A/B cable. Connect the DC1571A button (Figure 7) to begin reading the ADC. DC1571A SETUP DC Power is recommended for lower sample rates to divide down a higher frequency clock to the desired sample rate. The ratio The DC1571A requires 9V at approximately 100mA. DC of clock frequency to conversion rate is 80:1. If the clock Most of the supply current is consumed by the CPLD, op input is to be driven with logic, it is recommended that the amps, regulators and discrete logic on the board. The 9V DC 50 terminator (R5) be removed. Slow rising edges may input voltage powers the ADC through LT 1763 regulators compromise the SNR of the converter in the presence of which provide protection against accidental reverse bias. high amplitude higher frequency input signals. Additional regulators provide power for the CPLD and op amps. See Figure 1 for connection details. Data Output Clock Source Parallel data output from this board (0V to 3.3V default), if not connected to the DC718, can be acquired by a logic You must provide a low jitter 3.3V sine or square wave P-P analyzer, and subsequently imported into a spreadsheet, or to J1. The clock input is AC coupled so the DC level of the mathematical package depending on what form of digital clock signal is not important. A generator like the HP8644 signal processing is desired. Alternatively, the data can be or similar is recommended. Even a good generator can start fed directly into an application circuit. Use Pin 3 of J2 to to produce noticeable jitter at low frequencies. Therefore it dc1571afb 2