DEMO MANUAL DC1620A LTC2185, LTC2184, LTC2183, LTC2182, LTC2181, LTC2180, LTC2188, LTC2145-14/-12, LTC2144-14/-12, LTC2143-14/-12, LTC2142-14/-12, LTC2141-14/-12, LTC2140-14/-12, LTC2270: 16-/14-/12-Bit, 20Msps to 125Msps Dual ADCs DESCRIPTION Demonstration circuit 1620A supports a family of The versions of the 1620A demo board supporting the 16-/14-/12-bit, 20Msps to 125Msps ADCs. Each assembly LTC2185 and LTC2145 series of A/D converters are listed features one of the following devices: LTC 2185, LTC2184, in Table1. Depending on the required resolution and LTC2183, LTC2182, LTC2181, LTC2180, LTC2188, sample rate, the DC1620A is supplied with the appropri- LTC2145-14, LTC2144-14, LTC2143-14, LTC2142-14, ate ADC. The circuitry on the analog inputs is optimized LTC2141-14, LTC2140-14, LTC2145-12, LTC2144-12, for analog input frequencies from 5MHz to 70MHz. Refer LTC2143-12, LTC2142-12, LTC2141-12, or LTC2140-12, to the data sheet for proper input networks for different LTC2270 high speed, high dynamic range ADCs. input frequencies. Demonstration circuit 1620A supports the LTC2185/ Design files for this circuit board are available at LTC2145 family DDR LVDS output mode. DEMO MANUAL DC1620A (T = 25C) PERFORMANCE SUMMARY A PARAMETER CONDITION VALUE Supply VoltageDC1620A Depending on Sampling Rate and the A/D Converter Optimized for 4.5V 4.5V 6.0V Min/Max Provided, This Supply Must Provide Up to 500mA Analog Input Range Depending on SENSE Pin Voltage 1V to 2V P-P P-P Logic Input Voltages Minimum Logic High 1.3V Maximum Logic Low 0.6V Logic Output Voltages (Differential) Nominal Logic Levels (100 Load, 3.5mA Mode) 350mV/1.25V Common Mode Minimum Logic Levels (100 Load, 3.5mA Mode) 247mV/1.25V Common Mode Sampling Frequency (Convert Clock Frequency) See Table 1 Convert Clock Level Single-Ended Encode Mode (ENC Tied to GND) 0V to 3.6V Differential Encode Mode (ENC Not Tied to GND) 0.2V to 3.6V Resolution See Table 1 Input frequency range See Table 1 SFDR See Applicable Data Sheet SNR See Applicable Data Sheet QUICK START PROCEDURE Demonstration circuit 1620A is easy to set up to evaluate JP5-NAP: Enables and disables NAP mode (Default: the performance of the LTC2185/LTC2145 A/D converter disable) family. Refer to Figure 1 for proper measurement equip- JP6-LVDS/CMOS: Selects between LVDS and CMOS output ment setup and follow the procedure below: signaling. (Default: LVDS) Setup Applying Power and Signals to the DC1620A If a DC890 USB data acquisition and collection system Demonstration Circuit was supplied with the DC1620A demonstration circuit, If a DC890 is used to acquire data from the DC1620A, the follow the DC890 Quick Start Guide to install the required DC890 must first be connected to a powered USB port software and for connecting the DC890 to the DC1620A or provided an external 6V to 9V before applying +4.5V and to a PC. to +6.0V across the pins marked V+ and GND on the DC1620A. DC1620A requires 4.5V for proper operation. DC1620A Demonstration Circuit Board Jumpers Regulators on the board produce the voltages required for The DC1620A demonstration circuit board should have the ADC. The DC1620A demonstration circuit requires up the following jumper settings as default positions: (as to 500mA depending on the sampling rate and the A/D per Figure 1) converter supplied. JP2-PAR/SER: Selects Parallel or Serial programming The DC890 data collection board is powered by the USB mode. (Default: Serial) cable and does require an external power supply when collecting data from an LVDS demo board. It must be JP3-Duty Cycle Stabilizer: Enables/Disable Duty Cycle supplied from an external 6V to 9V on turrets G7(+) and Stabilizer. (Default: Enable) G1() or the adjacent 2.1mm power jack. JP4-SHDN: Enables and disables the LTC2185/LTC2145. (Default: Enable) dc1620afb 2