DC1646A Analog Devices

DEMO MANUAL DC1646A LTC5564 15GHz RF Power Detector with Comparator Description The demonstration circuit 1646A features the LTC 5564, an plans. The Demo Circuit Modification page provides the UltraFast RF peak detector with a built in gain-selectable design information required for modifying with this demo high speed operational amplifier and comparator. circuit 1646A. The 1646A demo circuit includes a simple impedance Design files for this circuit board are available at matching network that provides better than 10dB return DEMO MANUAL DC1646A q Uick st Art proce DU The VCC COMP (E11) test point is an alternative output Operation of V (J2 SMA connector). Install a 0 resistor COMP The demonstration circuit 1646A is preconfigured to work or a jumper to R3 will have the comparator Output at for applications at frequencies of 5.8GHz and 15GHz. It has VCC-COMP test point. better than 15dB return loss at these targeted frequencies. The input dynamic range at 5.8GHz is 40dB (from 24dBm Loading Bypass Capacitors to 16dBm) and slightly lower sensitivity at 15GHz. The LTC5564 has been designed to directly drive a capaci- tive load of 10pF at V . When driving a capacitive load Comparator OUT greater than 10pF a series resistance should be added The high speed comparator compares the external refer- between V and the load to maintain good stability. This OUT ence voltage on the V pin to the internal signal voltage REF resistance should be placed as close to V as possible. OUT V from the peak detector and produces the output logic P The demo board 1646A is loaded with R series = R6 = 0. signal V . V is the internal comparator positive input COMP P Refer to Table 2 for typical series resistor (R6) values for as shown in Figure 1 Simplified Block Diagram. various capacitive loads. The demo board has a typical 10mV hysteresis for its Table 2. Typical Series Resistor (R6) Values for V Capacitive comparator and its response time can be as fast as 9ns OUT Loading (10dBm input power step to V 50%) through out its COMP C R SERIES(R6) LOAD supporting frequencies. Up to 10pF 0 The, 1646A demo boards, LEN test point provides latch 11pF to 20pF 40 enable/disable functionality of the comparator. The com- 21pF to 100pF 68 parator is always enabling with the pulling down 10k resistor Greater Than 100pF 100 (R8) to ground. Connecting The LEN test point to V will CC place the comparator in the disable mode. Amplifier The R1 and R2 footprints are optional for configuring DC voltage of the V test point. The C1 is the ground coupling REF The high speed amplifier offers four gain settings and capacitor of the, R1 and R2, voltage divider. is capable of driving a 1.7mA load with an output swing range of approximately 295mV to V 1.6V. CC V V V CCRF CCA CCP The standard demonstration circuit 1646A has a unity gain. Therefore, the pins G0 and G1 (or the test point 250 RFIN Gain0 and Gain1) are pulling down for the logical Low with 8pF R10 = R11 = 10k resistors. The pins can be connected to V forming the logical High for others gains setting. CC 80A 1.2k Refer to Table 3 for gain setting operation. LEN V P + The V pin provides output DC offset adjustment OUTADJ V COMP V BIAS to satisfy various interface requirements. Setting V OUT V REF to 500mV also provides the maximum demodulation 1.6k V + OUTADJ 1.7k V bandwidth in each gain mode. OUT PROGRAMMABLE FEEDBACK ARRAY 200 200 The R9, R12 and C13 footprints are provided on the demo DC1664 F01 board to configure the V DC voltage. The R9 and OUTADJ PINS 3, 4, EXPOSED PAD PIN 17 R12 are forming voltage divider topology and the C13 G1 G0 is the ground coupling capacitor. Refer to the LTC5564 Figure 1. Simplified Block Diagram dc1646af 2 + re