DEMO MANUAL DC1762A LTC2165, LTC2164, LTC2163 LTC2162, LTC2161, LTC2160, LTC2159, LTC2269 16-Bit, 20Msps to125Msps ADCs Description Demonstration circuit 1762A supports a family of 16-Bit Depending on the required resolution and sample rate, 20Msps to 125Msps ADCs. Each assembly features one the DC1762A is supplied with the appropriate ADC. The of the following devices: LTC 2165, LTC2164, LTC2163, circuitry on the analog inputs is optimized for analog input LTC2162, LTC2161, LTC2160, LTC2159, or LTC2269 high frequencies from 5MHz to 140MHz. Refer to the data sheet speed, high dynamic range ADCs. for proper input networks for different input frequencies. Demonstration circuit 1762A supports the LTC2165 family Design files for this circuit board are available at DDR LVDS output mode. DEMO MANUAL DC1762A Quick s tart p D Demonstration circuit 1762A is easy to set up to evaluate DC1762 Demonstration Circuit Board Jumpers the performance of the LTC2165 A/D converter family. Refer The DC1762A demonstration circuit board should have to Figure 1 for proper measurement equipment setup and the following jumper settings as default positions: (as follow the procedure below: per Figure 1) Setup JP2 PAR/SER: Selects parallel or serial programming mode. (default: serial) If a DC890 USB demonstration circuit was supplied with the DC1762A demonstration circuit, follow the DC890 JP3 Duty Cycle Stabilizer: enables/disables duty cycle Quick Start Guide to install the required software and for stabilizer. (default: enable) connecting the DC890 to the DC1762A and to a PC. JP4 SHDN: Enables and disables the LTC2165. (default: enable) JP5 NAP: Enables and disables NAP mode. (default: enable) JP6 LVDS/CMOS: Selects between LVDS and CMOS output signaling. (default: LVDS) 4.5V TO 6V ANALOG INPUT PARALLEL DATA OUTPUT TO DC890 PARALLEL/SERIAL PROGRAMMING MODE DUTY CYCLE STABILIZER SHDN NAP LVDS/CMOS SINGLE-ENDED ENCODE CLOCK dc1762a F01 FROM DC1075 Figure 1. DC1762 Setup dc1762afb 2 ure roce