DEMO MANUAL DC1783A LTC2380/LTC2379/LTC2378/ LTC2377/LTC2376: 18-Bit/16-Bit, 2Msps/1.6Msps/1Msps/ 500ksps/250ksps Low Power, Low Noise ADCs DESCRIPTION The LTC2380/LTC2379/LTC2378/LTC2377/LTC2376 are performance such as peak-to-peak noise and DC linearity. low power, low noise ADCs with serial outputs that can Use the DC718 if precise sampling rates are required or to operate from a single 2.5V supply. The following text refers demonstrate AC performance such as SNR, THD, SINAD to the LTC2379-18 but applies to all parts in the family, and SFDR. The demonstration circuit 1783A is intended the only difference being the maximum sample rates and to demonstrate recommended grounding, component the number of bits. The LTC2379-18 supports a 5V fully placement and selection, routing and bypassing for this differential input range with a 101dB SNR, consumes ADC. Several suggested driver circuits for the analog only 18mW and achieves 2LSB INL max with no miss- inputs will be presented. ing codes at 18-bits. The DC1783A demonstrates the DC Design files for this circuit board are available at and AC performance of the LTC2379-18 in conjunction DEMO MANUAL DC1783A DESCRIPTION Table 1. DC1783A Assembly Options ASSEMBLY VERSION U1 PART NUMBER MAX CONVERSION RATE NUMBER OF BITS MAX CLK IN FREQUENCY DC1783A-A LTC2380CMS-16 2Msps 16 100MHz DC1783A-B LTC2378CMS-16 1Msps 16 50MHz DC1783A-C LTC2377CMS-16 500ksps 16 25MHz DC1783A-D LTC2376CMS-16 250ksps 16 12.5MHz DC1783A-E LTC2379CMS-18 1.6Msps 18 99.2MHz DC1783A-F LTC2378CMS-18 1Msps 18 62MHz DC1783A-G LTC2377CMS-18 500ksps 18 31MHz DC1783A-H LTC2376CMS-18 250ksps 18 15.5MHz QUICK START PROCEDURE DC718 DC590 SETUP Check to make sure that all switches and jumpers are IMPORTANT To avoid damage to the DC1783A, make set as shown in the connection diagram of Figure 1. The sure that V (JP6) is set to 3.3V before connecting the CCIO default connections configure the ADC to use the onboard DC590 to the DC1783A. reference and regulators to generate the required common To use the DC590 with the DC1783A, it is necessary to mode voltages. The analog input is DC-coupled. Connect apply 9V and ground to the 9V and GND terminals or the DC1783A to a DC718 USB High Speed Data Collection disable amplifier U15 by moving R32 and R36 to R31 and Board using connector J2. Then, connect the DC718 to a R38 respectively. If U15 is disabled, it is required that J4 host PC with a standard USB A/B cable. Apply 9V to the and J8 are both driven. If U15 is not disabled then it is indicated terminals. Then apply a low jitter signal source only necessary to drive J4. Connect the DC590 to a host to J4. The default setup uses a single-ended to differential PC with a standard USB A/B cable. Connect the DC1783A converter so that it is only necessary to apply a single-ended to a DC590 USB serial controller using the supplied input signal to J4. Connect a low jitter 100MHz 3.3V P-P 14-conductor ribbon cable. Apply a signal source to J4 or sine wave or square wave to connector J1. Note that J1 J4 and J8 depending on how the DC1783A is configured. has a 50 termination resistor to ground. Run the evaluation software supplied with the DC590 or Run the PScope software (PScope.exe version K72 or download it from www.linear.com. The correct control later) supplied with the DC718 or download it from www. panel will be loaded automatically. Click the COLLECT linear.com. button (Figure 7) to begin reading the ADC. Complete software documentation is available from the Help menu. Updates can be downloaded from the Tools DC1783A SETUP menu. Check for updates periodically as new features may be added. DC Power The PScope software should recognize the DC1783A and The DC1783A requires 9VDC and draws 100mA. Most configure itself automatically. of the supply current is consumed by the CPLD, opamps, regulators and discrete logic on the board. The 9VDC Click the COLLECT button (See Figure 6) to begin acquiring input voltage powers the ADC through LT1763 regulators data. The Collect button then changes to Pause, which can which provide protection against accidental reverse bias. be clicked to stop data acquisition. Additional regulators provide power for the CPLD and opamps. See Figure 1 for connection details. dc1783afb 2