DEMO MANUAL DC1796A LTC6360 Driving 18-Bit SAR ADC Description The LTC 6360 is a very low noise, high precision, high Demonstration circuit 1796A demonstrates the DC and speed amplifier, suitable for driving SAR ADCs. The AC performance of the LTC6360 driving the LTC2369-18 LTC6360 features a total output noise of 2.3nV/Hz com- in conjunction with the DC590B QuikEval and DC718 bined with 150ns settling time to 16-bit levels (A = 1). fast DAACS data collection boards. Use the DC590B to V demonstrate DC performance such as peak-to-peak noise While powered from a single 5V supply, the amplifier output and DC linearity. Use the DC718 if precise sampling rates can swing to 0V while maintaining high linearity. This is are required or to demonstrate AC performance, such as made possible with the inclusion of a very low noise on- SNR, THD, SINAD and SFDR. The demonstration circuit chip charge pump that generates a negative voltage to bias 1796A is intended to demonstrate recommended ground- the output stage of the amplifier, increasing the allowable ing, component placement and selection, routing and negative voltage swing. The LTC2370/LTC2369/LTC2368/ bypassing for the LTC6360 and the ADC. LTC2367/LTC2364 are low power, low noise ADCs with serial outputs that can operate from a single 2.5V supply. Design files for this circuit board are available at DEMO MANUAL DC1796A a Bly o Table 1. DC1796A Assembly Options ASSEMBLY VERSION U1 PART NUMBER MAX CONVERSION RATE NUMBER OF BITS MAX CLKIN FREQUENCY DC1796A-A LTC2370CMS-16 2Msps 16 100MHz DC1796A-B LTC2368CMS-16 1Msps 16 50MHz DC1796A-C LTC2367CMS-16 0.5Msps 16 25MHz DC1796A-D LTC2364CMS-16 0.25Msps 16 12.5MHz DC1796A-E LTC2369CMS-18 1.6Msps 18 99.2MHz DC1796A-F LTC2368CMS-18 1Msps 18 62MHz DC1796A-G LTC2367CMS-18 0.5Msps 18 31MHz DC1796A-H LTC2364CMS-18 0.25Msps 18 15.5MHz Quick s tart p D This board is tested by measuring the distortion at sion rate for an 18-bit SAR ADC). Refer to the Clock 1dBFS, 2kHz single-ended input, as shown in Figure 2. Source section for more detailed information. Set the clock amplitude to 3.3V . PP A low noise, low distortion generator such as Audio Pre- cision SYS-2722, B&K Type 1051 or Stanford Research 4. For best SNR measurement data, a 2.3kHz cutoff fre- DS360, should be used for SINAD, THD or SNR testing. quency lowpass filter is used in the input signal at J2. A low jitter RF oscillator, such as the Marconi Instruments See the Analog Input section for more details. Multisource Generator 2026, should be used as the clock 5. Apply a 2kHz, 1dBFS signal to connector J2. There are source. several ways of level shifting the input signal. In this To test the boards follow the steps below: case, the V /2 turret on the demo board was used to REF provide level shifting of the input signal. V /2 should REF 1. Make sure that all the jumpers are set as shown in be properly bypassed to ground to minimize noise on Figure 2 (DC1796A test diagram). the input signal. 2. Power up the board by applying +9VDC. The performance that results from these connections is 3. Apply the clock signal to connector J1. Set the clock displayed in Figure 7. frequency to 99.2MHz (to achieve a 1.6Msps conver- dc1796af 2 ure roce ptions ssem