DEMO MANUAL DC1826A LTC2389 18-Bit/16-Bit, 2.5Msps Low Noise, SAR ADCs with Pin-Configurable Analog Input Range DESCRIPTION Demonstration circuit 1826A features the LTC 2389 low The DC1826A demonstrates the performance of the noise, high speed successive approximation register ADC LTC2389-18 in conjunction with the DC718 QuikEval II which operates from a single 5V supply. The following data collection board. text refers to the LTC2389-18, but also applies to the The demonstration circuit 1826A is intended to demon- LTC2389-16, the only difference being the number of bits. strate recommended grounding, component placement The LTC2389-18 supports pin-configurable fully differential and selection, routing and bypassing for this ADC. Several (4.096V), pseudo-differential unipolar (0V to 4.096V), and suggested driver circuits for the analog inputs will be pseudo-differential bipolar (2.048V) analog input ranges, presented. allowing it to interface with multiple signal chain formats. Design files for this circuit board are available at The LTC2389-18 achieves 2.5LSB INL (maximum), with DEMO MANUAL DC1826A DC1826A ASSEMBLY OPTIONS ASSEMBLY VERSION U1 PART NUMBER MAX CONVERSION RATE NUMBER OF BITS SERIAL MAX CLKIN FREQUENCY DC1826A-A LTC2389CMS-18 2.5Msps 18 100MHz DC1826A-E LTC2389CMS-16 2.5Msps 16 100MHz DC718 QUICK START PROCEDURE Check to ensure that all switches and jumpers are set as Run the QuikEval II software (PScope.exe version K73 or shown in the connection diagram of Figure 1. The default later) supplied with the DC718 or download it from www. connections configure the ADC to use the onboard refer- linear.com. ence and regulators to generate the required common Complete software documentation is available from the mode voltages. The analog input is DC-coupled. Connect help menu. Updates can be downloaded from the tools the DC1826A to a DC718 USB high speed data collection menu. Check for updates periodically as new features board using connector J4. Then, connect the DC718 to may be added. a host PC with a standard USB A/B cable. Apply 9V to The PScope software should recognize the DC1826A the indicated terminals. Then, apply a low jitter signal and configure itself automatically. source to J2. The default setup uses a single-ended to differential converter so that it is only necessary to apply Click the collect button (see Figure 7) to begin acquiring a single-ended input signal to J2. Connect a low jitter data. The collect button then changes to pause, which can 2.5MHz (100MHz for serial) 3.3V sine wave or square P-P be clicked to stop data acquisition. wave to connector J1 for parallel operation. Note that J1 has a 49.9 termination resistor to ground. DC1826A SETUP DC Power Clock Source The DC1826A requires 9V and draws 100mA. Most You must provide a low jitter 3.3V sine or square DC P-P of the supply current is consumed by the CPLD, opamps, wave to J1. The clock input is AC-coupled so the DC level of the clock signal is not important. A generator regulators and discrete logic on the board. The 9V in- DC like the HP8644 or the DC1216A-A is recommended. put voltage powers the ADC through LT1763 regulators Even a good generator can start to produce noticeable which provide protection against accidental reverse bias. jitter at low frequencies. Therefore, it is recommended Additional regulators provide power for the CPLD and for lower clock rates to divide down a higher frequency opamps. See Figure 1 for connection details. clock to the desired sample rate. For serial operation, the ratio of clock frequency to conversion rate is 50:1. The maximum serial conversion rate is 2Msps. If the clock input is to be driven with logic, it is recommended that dc1826afa 2