DC1835A Analog Devices

DC1835A May 30, 2014 LTC6803-4 Battery Monitor HARDWARE/SOFTWARE DEMONSTRATION BOARD MANUAL DESCRIPTIONB0 Evaluation circuit DC1835A is a Battery Monitoring LTC6803-4 KB1 EY FEATURES System to demonstrate the functional operation of the Separate Cell 0 ADC input (bottom-cell connection). LTC6803-4 integrated circuit. The design includes the Conversion range down to 300mV per cell. ability to bus up to 10 devices with built-in board-to- Addressable SPI interface (up to 16 devices). board ribbon-cable interconnects and selectively apply Packet Error Checking on command writes. resistive loading to any cell for purposes of Passive 6X lower standby current than LTC6802. Balancing. Additionally, the board includes a DC-DC Power-down mode for no battery drain. boost conversion section to power the IC from an iso- Active pullup on discharge-control outputs (S pins). lated external 5V supply. The external 5V supply also Extensive diagnostic commands. powers a data isolator so that the user SPI data bus is floating with respect to the monitored cells. DC1835A DEMO FEATURES B2 Fully isolated data and power interface- no powering from cells. On-board 54V boost supply. CELLS CONNECTOR (SEPARABLE) Controllable discharging for Passive Balancing. Graphical User Interface (GUI) screen for demon- stration of new features and program code devel- opment. Dual SPI connectors for interconnecting multiple DISCHARGE SWITCHES boards DC-DC LTC6803-4 BOOST SPI DATA & SPI ADDRESS INPUT POWER OUTPUT BITS ISOLATOR DC1835A GETTING STARTED W3B ITH ONE BOARD CONNECTED 5BSINGLE BOARD CONNECTION TO PC AND GUI Step 1. Set jumpers on DC1835A to the default posi- tions indicated in Table 1. 6BTABLE 1. JUMPER FUNCTIONS JUMPER FUNCTION DEFAULT DEFAULT POSITION ALTERNATIVE POSITION POSITION Top of Stack (TOS) 1 Indicates that the cells monitored by the Forces device into the secondary toggle polling JP1 board are at the top of the battery stack to mode. provide primary toggle polling. Only one de- vice should form the toggle frequency. JP2-JP5 A0, A1, A2, A3 0 Sets hexadecimal address nibble to 0x0 Setting bits to 1 configures different device (address) addresses, Used in the event there are multiple LTC6803-4 in a SPI bus. +5V Source EXT Power is furnished by the External 5V turret Power is taken from the SPI BUS IN connec- JP6 connections. tion. Step 2. Connect an un-energized 5V supply to the Ex- A DC590B board has a required pull-up resistor for ternal 5V power turrets (labeled EXT +5V and the SDO line already connected. If a system other HOST GND). The supply will have the same ground than DC590 is driving the SPI interface, there potential as the ribbon signals in the SPI bus. must be a pull-up resistor installed in location R60 (0603 size, 2K to 5K is suitable). This Step 3. Power up 5V supply. Current draw should be pull-up resistor was not added to the DC1835A be- about 22mA. cause it would demand too much drive current for Step 4. Connect DC590B Quick Eval USB cable to bussed operation on a multiple board setup. PC/Laptop USB port. Connect ribbon cable from Step 5. Connect the cells to be monitored to the cells DC590B to the SPI BUS IN port of DC1835A (H1). connector J1. This connector is in two pieces. The Make sure that the driver for DC590B has been setscrew piece can be unplugged to make it safer downloaded from www.linear.UH comU and instH alled on to attach wiring from a three to twelve cell battery the computer. This can be verified by running stack. The LTC6803-4 is intended to measure from Quick Eval and seeing the message that there is a three to twelve individual cells with a total stack missing module for this board type. Close the voltage of 9V to 51V. Quick Eval program and then launch only the con- trol program: With fewer than 12 cells to be monitored, the bot- tom cell of the stack should always be connected LTC6803-2-4 GUI Vxx yyyymmdd.exe as Cell 1 between terminals J1-5(+cell contact) and When the DC590B Quick Eval board recognizes the J1-4(-cell contact). Terminal J1-4, is the Cell 0 ref- String ID code from the DC1835A board, the pro- erence point for the battery cell stack. The second gram will open and present the control screen. cell on the stack connects between terminals J1- This sometimes requires two launches of the GUI 6(+cell contact) and J1-5(-cell contact). All higher program to properly initialize. numbered terminals on J1 not used for cell con- nections may be shorted together with the top po- 2