DEMO MANUAL DC2062A LT4363-1/LT4363-2 12V Systems ISO-7637-2 Surge Stopper Description Demonstration circuit 2062A showcases the LT 4363 surge Board Layout stopper in a 12V, 3A ISO-7637-2 application. Inputs of up DC2062A is designed to withstand load dump. This high to 50VDC and load dumps of up to 100V are limited to voltage is stood off by RUV4, ROV4, R7, RLED2, Q1, Q4. 25V at the output. The MOSFET is protected against output Maximum input voltage is limited by Q1s 100V BV DSS overloads by current limiting. Sustained overvoltage or rating. The permissible time at 100V is limited by MOS- overcurrent conditions cause the LT4363 to turn off after FET safe operating area (SOA) and R7, which dissipates a timer delay. The LT4363-1 (DC2062A-A) latches off slightly less than 1.2W and is capable of doing so for at and is reset by pulling SHDN low for at least 100s. The least 500ms. LT4363-2 (DC2062A-B) automatically retries after a cool The minimum spacing is limited by 1206 pad spacing down delay retry is inhibited if OV is higher than 1.275V. where the gap between solder pads is 2mm, or just under Danger High voltage testing should be performed by 80mils. Thus, the spacing between the input plane and all qualified personnel only. As a safety precaution at least other board traces is maintained at a minimum of 2mm. two people should be present during high voltage testing. As a point of reference, a 2mm needle gap in air breaks L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear down well above 1kV. Technology Corporation. All other trademarks are the property of their respective owners. Design files for this circuit board are available at DEMO MANUAL DC2062A Quick s p D ISO-7637-2 Compliance 1) The power ratings only apply for operation in triode and when the DUT is mounted on an infinite heat sink. 2) The DC2062A is fully compatible with electrical transients The power capability of a MOSFET reduces significantly in a 12V ISO-7637-2 system. Compliance testing was when it is operated in saturation with a high V across it. DS performed by a third party company called TUV. Tests were performed at level 4, which is the most extreme MOSFET manufacturers provide an SOA graph which condition an ISO-7637-2 system can face. The compli- depicts the voltage and current conditions under which a ance report can be found on the sidebar of the LT4363 MOSFET can be expected to operate safely. When select- product landing page. ing MOSFETs for a surge stopper application this graph must always be consulted carefully due to the fact that A summary of the report is shown in Table 1. the points on the graph were tested under the previously discussed conditions. Load Dump Ride Through The DC2062A showcases the ability of the LT4363 to ride Reverse Input Protection through and suppress a 100V load dump pulse. While The DC2062A features reverse protection circuitry that the DC2062A can ride through load dump events, several protects downstream components from reverse transients points should be kept in mind. First, the dissipation of of up to 150V. This number is limited by the BV of DSS several components rises to significant levels during a Q2. The reverse protection circuitry also protects against load dump event. Since this event lasts for approximately reverse DC voltage of up to 30V. 500ms, these components are dissipating power for an appreciable amount of time. RUV4 dissipates 200mW, DC2062A-A and DC2062AB Options ROV4 dissipates 60mW, D1 dissipates 3.2W and R7 dis- The DC2062A-A is fitted with the LT4363-1 which latches sipates nearly 1.2W. These components are dissipating off after a timer delay in the presence of overvoltage or power for the duration of the 100V pulse and have been overcurrent conditions. Once latched off the LT4363-1 rated appropriately. may be restarted by pulsing the SHDN pin low for at least Another consideration is MOSFET SOA. Q1 dissipates 100s, or by briefly cycling power. an average of 80W throughout the time it is regulat- The DC2062A-B is fitted with the LT4363-2 which auto- ing a load dump pulse. While many modern MOSFETs matically retries after a cool-down cycle. Retry is inhibited have advertised power ratings much higher than 80W, by the OV pin, if the input is greater than 20V. Cool down these ratings are not indicative of performance in time is typically 22.8 seconds. surge stopper applications for the following reasons: Table 1. TUV ISO-7637 Report Summary CLASSIFICATION OF FUNCTIONAL STATUS DEVIATION TEST LEVEL IV OF PULSES/ WITHIN DOES NOT NOT PULSE REQUIREMENTS LEVEL PASSED DURATION NO DEVIATION SPECIFICATION COMPLY PERFORMED 1 100V 100V 5000 Pulses q Class A n Class A q q 2a +50V +50V 5000 Pulses n Class A q Class A q q 2b +10V +10V 10 Pulses q Class A n Class A q q 3a 150V 150V 1 Hour n Class A q Class A q q 3b +100V +100V 1 Hour n Class A q Class A q q 4 7V 7V 3 Pulse q Class A n Class A q q 5 +87V +89V 3 Pulse n Class A q Class A q q dc2062af 2 ure roce tart