DC2077A Analog Devices

DEMO MANUAL DC2077A LTC6431-20 50 20dB Gain Block IF Amplifier DESCRIPTION Demonstration circuit 2077A features the LTC 6431-20 amplifier for various applications. The LTC6431-20 pro- 50 gain block IF amplifier. The LTC6431-20 has a power vides 50 single-ended input and output impedances so gain of 20.8dB and it is part of the LTC6431-YY amplifier that it can be easily evaluated with most RF test equipment. series. Design files for this circuit board are available at The DC2077A demo board supports the LTC6431-YY am- DEMO MANUAL DC2077A PERFORMANCE SUMMARY T = 25C, V = 5V A CC Table 1. Typical Demo Board Performance Summary SYMBOL PARAMETER CONDITIONS VALUE / UNIT Power Supply V Operating Supply Range All V Pins Plus OUT 4.75V to 5.25V CC CC I Current Consumption Total Current 95mA CC OUTPUT OUTPUT THIRD-ORDER THIRD-ORDER SECOND OUTPUT 1DB INTERCEPT INTERMODU- HARMONIC THIRD HARMONIC COMPRESSION 1 1 2 2 3 FREQUENCY POWER GAIN POINT LATION DISTORTION DISTORTION POINT NOISE FIGURE (MHZ) S21 OIP3 OIM3 HD2 HD3 P1DB NF 100 20.2 47.2 90.4 56.8 96.7 23.2 3.2 200 20.6 48.0 91.9 55.6 92.9 22.4 2.7 240 20.6 47.9 91.9 52.5 106.1 22.0 2.7 300 20.7 47.9 91.9 50.5 83.1 21.8 2.8 400 20.6 46.9 89.9 50.4 77.4 21.7 2.8 500 20.6 45.0 86.0 47.8 72.6 21.8 2.9 600 20.6 42.5 81.0 43.7 64.0 21.7 3.1 700 20.5 39.7 75.5 42.1 60.7 21.4 3.3 800 20.5 38.6 73.1 40.6 63.1 21.4 3.4 900 20.5 37.1 70.3 37.1 60.4 21.1 3.7 1000 20.4 36.0 68.0 36.9 55.1 20.8 3.8 1100 20.3 35.1 66.2 35.7 54.5 20.4 3.9 1200 20.2 34.4 64.8 34.4 53.6 20.3 4.1 Units dB dBm dBc dBc dBc dBm dB Notes: All figures are referenced to J1 (Input Port) and J2 (Output Port). 1. Two-tone test conditions: Output power level = +2dBm/tone, tone spacing = 1MHz. 2. Single-tone test conditions: Output power level = +6dBm. 3. Small-signal noise figure. OPERATION The demo circuit 2077A is a high linearity, fixed gain L2 and C6 are optional parts. These additional components amplifier. It is designed for ease of use. Both the input allow for further optimization to lower or wider frequency and output are internally matched to 50 single-ended range applications. source and load impedance. Figure 2 shows the DC2077As A parallel 62pF (C2) and 348 (R1) input network has S-parameters. been added to ensure low frequency stability. Note that the Figure 4 shows the demo circuits schematic. The input and input stability network does degrade performance below output DC blocking capacitors (C1 and C7) are required 150MHz. Low frequency performance can be improved because this device is internally DC biased for optimal by increasing the value of capacitor C2. operation. The frequency appropriate choke (L1) and the The T DIODE Pin (Turret E1) can be forward biased to decoupling capacitors (C3 and C4) provide the proper ground with 1mA of current. The measured voltage will DC bias to the RF output node. Only a single 5V supply is be an indicator of the chip junction temperature (T ). J necessary for the VCC pins on the device. dc2077af 2