DEMO MANUAL DC2222A LTC2500-32/LTC2508-32/LTC2512-24: 32-Bit/24-Bit Oversampling ADCs with Configurable Digital Filter Description Demonstration circuit 2222A features the LTC 2500-32, and DC linearity. Use the DC890 if precise sampling rates LTC2508-32 and LTC2512-24 ADCs. The LTC2500-32, are required or to demonstrate AC performance such as LTC2508-32 and LTC2512-24 are low power, low noise, SNR, THD, SINAD and SFDR. The DC2222A is intended high speed, 32-bit/24-bit SAR ADCs with an integrated con- to show recommended grounding, component placement figurable digital averaging filter that operate from a single and selection, routing and bypassing for this ADC. 2.5V supply. The following text refers to the LTC2508-32 Design files for this circuit board including the but applies to all parts, the only difference being sample schematic, BOM and layout are available at rate and number of bits. The DC2222A demonstrates the DEMO MANUAL DC2222A Quick s tart p D Table 1. DC2222A Assembly and Clock Options ASSEMBLY MAX OUTPUT MAX CLK IN VERSION U1 PART NUMBER DATA RATE DF BITS FREQ OUTPUT MODE DIVIDER DC2222A-A LTC2500IDKD-32 175ksps 4 32 70MHz A No Verify 100 173ksps 4 32 70MHz A Verify 101 250ksps 4 32 43MHz A Distributed Read 43 250ksps 4 32 45MHz A Verify + Dis. Read 45 800ksps 1 24 80MHz B 100 DC2222A-B LTC2508IDKD-32 3.472ksps 256 32 80MHz A No Verify 90 2.900ksps 256 32 75MHz A Verify 101 3.906ksps 256 32 43MHz A Distributed Read 43 3.906ksps 256 32 45MHz A Verify + Dis. Read 45 900ksps 1 14 90MHz B 100 DC2222A-C LTC2512IDKD-24 350.877ksps 4 24 80MHz A No Verify 57 303.03ksps 4 24 80MHz A Verify 66 400ksps 4 24 62.4MHz A Distributed Read 39 400ksps 4 24 70.4MHz A Verify + Dis. Read 44 1.5Msps 1 14 85.5MHz B 57 Check to make sure that all jumpers are set as described Run the PScope software (PScope.exe version K86 or in the DC2222A Jumpers section. In particular, make sure later) supplied with the DC890 or download it from www. that VCCIO (JP3) is set to the 2.5V position. Controlling linear.com/software. the DC2222A with the DC890 while JP3 of the DC2222A Complete software documentation is available from the is in the 3.3V position will cause noticeable performance Help menu. Updates can be downloaded from the Tools degradation in SNR and THD. The default jumper con- menu. Check for updates periodically as new features nections configure the ADC to use the onboard reference may be added. and regulators. The analog input is DC coupled by default. The PScope software should recognize the DC2222A Connect the DC2222A to a DC890 USB High Speed Data and configure itself automatically. The default setup is to Collection Board using connector P1. (Do not connect a read the filtered output with Verify and Distributed Read PScope controller and QuikEval controller at the same not selected and the Down Sampling Factor (DF) set to time.) Next, connect the DC890 to a host PC with a stan- the smallest possible value. To change this, click on the dard USB A/B cable. Apply 9V to the indicated terminals. Set Demo Bd Options setting of the PScope Tool Bar as Next apply a low jitter differential sine source to J2 and J4. shown in Figure 2. The Configuration Options box shown Connect a low jitter 2.5V sine wave or square wave to P-P in Figures 3a, 3b and 3c allows the ADC output, DF, Verify connector J1, using Table 1 as a guide for the appropriate and Distributed Read to be set. In the case of the LTC2500 clock frequency. Note that J1 has a 49.9 termination it is also possible to select the filter type, gain compres- resistor to ground. sion and gain expansion. If Verify is not selected then the dc2222afa 2 ure roce