DC2470A Analog Devices

LTC4284 High Power Negative Voltage Hot Swap Controller with Energy Monitor FEATURES DESCRIPTION n Drives Two Gates for High Power Applications The LTC 4284 negative voltage hot swap controller drives n Configurable Parallel, Staged Start or Single Modes external N-channel MOSFETs to allow a board to be safely n Protects MOSFET with SOA Timer inserted and removed from a live backplane. The dual- n gate, multi-mode drivers optimize the MOSFET safe oper- Programmable 15mV to 30mV Current Limit Sense ating area (SOA) for a variety of power levels. The SOA Voltage with <3.3% Accuracy and Adjustable Foldback n timer limits MOSFET temperature rise for reliable protec- 8-Bit to 16-Bit Gear-Shift ADC with 0.7% Accuracy n tion against overstresses. Monitors Voltages, Currents, Power and Energy n Nonvolatile Configuration and Fault Recording 2 An I C interface and onboard gear-shift ADC allow moni- n Floating Topology for Rugged High Voltage Operation toring of board current, voltage, power, energy, and fault n Selectable Inrush Control: dV/dt or Current Limit status. An available single-wire broadcast mode simplifies 2 n I C/SMBus or Single-Wire Broadcast Interfaces the interface by eliminating two isolators. The included n Min/Max ADC Measurement Logging with Alerts EEPROM provides black-box capturing and nonvolatile 2 n Reboots on I C Command with Programmable Delay configuration of fault behavior. n Adjustable Input UV/OV Thresholds and Hysteresis Additional features respond to input UV/OV, interrupt the n 44-Pin 5mm 8mm QFN Package host when a fault has occurred, notify when output power is good, detect insertion of a board, turn off the MOSFETs APPLICATIONS if an external supply monitor fails to indicate power good n within a timeout period, and auto-reboot after a program- Telecom Infrastructure mable delay following a host commanded turn-off. n 48V Distributed Power Systems n Servers and Data Centers All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 8230151, 7382167, 9634480, 9634481, 10263414. n Power Monitors TYPICAL APPLICATION 52V/2500W Hot Swap Controller with Telemetry RTN Startup Behavior 4 1k IN SERIES 316k 1F 0.1F RTN 0.25W EACH (SHORT PIN) + V V EE EE 10.2k 402k GATE1 10V/DIV INTV MODE V V RTNS CC Z IN V EE UVH V LOAD SCL UVL SDAI 7.68k SDAO GATE2 OV ALERT 10V/DIV 2000F 4 LTC4284 TMR ADIN 4 RAMP ADIO 52V EN 4 10k PGIO V 470nF OUT V EE DRNS 50V/DIV + + SENSE2 SENSE1 SENSE1 SENSE2 GATE1 GATE2 DRAIN 10.2k I INRUSH 2.2nF 1A/DIV 100k V EE V EE 316k 4284 TA01b 5m 100ms/DIV 52V V OUT INPUT PSMN7R6-100BSE UV = 43.5V UV RELEASE AT 48.5V 0.33m OV = 59V 4284 TA01a OV RELEASE AT 58V 2 IPT020N10N3 Rev. B 1 Document Feedback For more information www.analog.comLTC4284 TABLE OF CONTENTS Features ..................................................... 1 Resetting Faults ......................................................39 Applications ................................................ 1 Alarms ....................................................................39 Typical Application ........................................ 1 EN Pin ...................................................................39 Description.................................................. 1 ON Bit .....................................................................39 Absolute Maximum Ratings .............................. 3 Turning the LTC4284 On and Off ............................40 Order Information .......................................... 3 Configuring PGIO and ADIO Pins ............................ 41 Pin Configuration .......................................... 3 Design Examples .................................................... 41 Electrical Characteristics ................................. 4 Example 1: Design Procedure of Parallel Mode with 2 I C Timing Diagram ....................................... 9 SOA Timer and Current Limit Startup ..................... 41 Typical Performance Characteristics ................... 9 Example 2: Design Procedure of Low Stress Staged Pin Functions .............................................. 12 Start Mode with Single Capacitor on TMR Pin and Block Diagram ............................................. 16 dV/dt Startup ..........................................................45 Operation................................................... 17 Layout Considerations ............................................49 2 Applications Information ................................ 18 Reboot on I C Command ........................................49 Input Power Supply ................................................ 18 Data Converters ......................................................49 Turn-On Sequence ..................................................20 EEPROM .................................................................53 Inrush Control .........................................................22 Fault Log .................................................................54 Power Good Monitors and PGI Fault .......................23 Digital Interface ......................................................55 Turn-Off Sequence .................................................. 24 Bus Compatibility ....................................................55 Overcurrent Protection ........................................... 24 START, REPEATED START and STOP Conditions ...56 SOA Timer .............................................................. 24 ACK/NACK ..............................................................56 2 Overcurrent Fault and Auto-Retry ...........................27 I C Device Addressing ............................................56 Current Limit Adjustment ........................................27 Transfer Protocol Types ..........................................56 Current Limit Foldback ............................................27 Command Codes and Register Addressing .............58 FET Bad Fault and Auto-Retry .................................28 Write Protocols .......................................................58 Input Step and Optimum Output Ramp ...................29 Read Protocols .......................................................58 Dual-Gate Operation Modes ....................................30 Read Page and Write Page Protocols .....................58 Parallel Mode (Mode 2) ..........................................30 Byte Ordering .........................................................58 High Stress Staged Start Mode (Mode 3) ...............32 ALERT and Alert Response Protocol .....................58 Low Stress Staged Start (Mode 4) .........................34 Stuck Bus Reset .....................................................59 Single Driver Mode (Mode 1) ..................................35 Data Synchronization and Arbitration .....................59 Overvoltage Fault and Auto-Retry ...........................36 Single-Wire Broadcast ............................................60 Undervoltage Fault and Auto-Retry .........................37 Register Tables .......................................................62 FET Short Fault .......................................................38 Package Description ..................................... 80 Power Failed Fault ...................................................38 Revision History .......................................... 81 External Fault and Auto-Retry .................................38 Typical Application ....................................... 82 Cooling Delay ..........................................................38 Related Parts .............................................. 82 Rev. B 2 For more information www.analog.com