LTC4283 Negative Voltage Hot Swap Controller with Energy Monitor FEATURES DESCRIPTION n Allows Safe Insertion into Live 48V Backplanes The LTC 4283 negative voltage hot swap controller drives n Protects MOSFET with SOA Timer an external N-channel MOSFET to allow a board to be n Programmable 15mV to 30mV Current Limit Sense safely inserted and removed from a live backplane. The device features programmable current limit with foldback Voltage with <3.3% Accuracy and Adjustable Foldback n and independently adjustable inrush current to optimize 8-Bit to 16-Bit Gear-Shift ADC with 0.7% Accuracy n the MOSFET safe operating area (SOA). The SOA timer Monitors Voltages, Currents, Power and Energy n limits MOSFET temperature rise for reliable protection Nonvolatile Configuration and Fault Recording n against overstresses. Floating Topology for Rugged High Voltage Operation n Selectable Inrush Control: dV/dt or Current Limit 2 An I C interface and onboard gear-shift ADC allow moni- 2 n I C/SMBus or Single-Wire Broadcast Interfaces toring of board current, voltage, power, energy, and fault n Min/Max ADC Measurement Logging with Alerts status. An available single-wire broadcast mode simplifies 2 n Reboots on I C Command with Programmable Delay the interface by eliminating two isolators. The included n Adjustable Input UV/OV Thresholds and Hysteresis EEPROM provides black-box capturing and nonvolatile n 38-Pin 5mm 7mm QFN Package configuration of fault behavior. Additional features respond to input UV/OV, interrupt the APPLICATIONS host when a fault has occurred, notify when output power n is good, detect insertion of a board, turn off the MOSFET Telecom Infrastructure n if an external supply monitor fails to indicate power good 48V Distributed Power Systems within a timeout period, and auto-reboot after a program- n Servers and Data Centers mable delay following a host commanded turn-off. n Power Monitors All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 8230151, 7382167, 9634480, 9634481, 10263414. TYPICAL APPLICATION 48V/600W Hot Swap Controller with Telemetry RTN UV = 38.6V 41k IN SERIES 200k 1F 0.1F LTC4283 Startup Behavior 0.25W EACH UV RELEASE AT 43.1V OV = 71.9V RTN V V EE EE OV RELEASE AT 70.7V CONTACT (SHORT PIN) 5.11k BOUNCE 487k 48V INPUT INTV V V RTNS CC Z IN V EE + 50V/DIV UVH SCL UVL SDAI V LOAD 14.3k SDAO RAMP V OUT 50V/DIV ALERT OV LTC4283 18.2k 500F TMR 4 ADIN V GATE 4 128ms DEBOUNCE EN ADIO 10V/DIV 1.13M 4.7nF 4 V EE PGIO 10k I INRUSH + 68nF SENSE SENSE GATE DRAIN DRNS 5A/DIV 470 5.11k 4283 TA01b V V EE EE 25ms/DIV 100k 100nF 200k V EE 48V V OUT INPUT PSMN4R8-100BSE 2 4283 TA01a 0.5m Rev. B 1 Document Feedback For more information www.analog.comLTC4283 TABLE OF CONTENTS Features ..................................................... 1 EN Pin ...................................................................32 Applications ................................................ 1 ON Bit .....................................................................32 Typical Application ........................................ 1 Turning the LTC4283 On and Off ............................33 Description.................................................. 1 Configuring PGIO and ADIO Pins ............................33 Absolute Maximum Ratings .............................. 3 Design Examples ....................................................34 Order Information .......................................... 3 Example 1: Design Procedure for Systems with Large Pin Configuration .......................................... 3 Input Steps .............................................................34 Electrical Characteristics ................................. 4 Example 2: Design Procedure for Systems with 2 I C Timing Diagram ....................................... 9 Regulated Inputs .....................................................38 Typical Performance Characteristics .................. 10 Layout Considerations ............................................ 41 2 Pin Functions .............................................. 13 Reboot on I C Command ........................................ 41 Block Diagram ............................................. 16 Data Converters ......................................................42 Operation................................................... 17 EEPROM .................................................................45 Applications Information ................................ 18 Fault Log .................................................................46 Input Power Supply ................................................ 18 Digital Interface ...................................................... 47 Turn-On Sequence ..................................................20 Bus Compatibility .................................................... 47 Inrush Control .........................................................22 START, REPEATED START and STOP Conditions ...48 Power Good Monitors and PGI Fault .......................23 ACK/NACK ..............................................................48 2 Turn-Off Sequence ..................................................23 I C Device Addressing ............................................48 Overcurrent Protection ........................................... 24 Transfer Protocol Types ..........................................48 SOA Timer .............................................................. 24 Command Codes and Register Addressing .............50 Overcurrent Fault and Auto-Retry ...........................26 Write Protocols .......................................................50 Current Limit Adjustment ........................................27 Read Protocols .......................................................50 Current Limit Foldback ............................................27 Read Page and Write Page Protocols .....................50 FET Bad Fault and Auto-Retry .................................28 Byte Ordering .........................................................50 Input Step and Optimum Output Ramp ...................29 ALERT and Alert Response Protocol .....................50 Overvoltage Fault and Auto-Retry ...........................29 Stuck Bus Reset ..................................................... 51 Undervoltage Fault and Auto-Retry .........................30 Data Synchronization and Arbitration ..................... 51 FET Short Fault .......................................................31 Single-Wire Broadcast ............................................52 Power Failed Fault ...................................................31 Register Tables .......................................................54 External Fault and Auto-Retry .................................31 Package Description ..................................... 72 Cooling Delay ..........................................................31 Revision History .......................................... 73 Resetting Faults ......................................................32 Typical Application ....................................... 74 Alarms ....................................................................32 Related Parts .............................................. 74 Rev. B 2 For more information www.analog.com