DEMO MANUAL DC2588A LTC2387/LTC2386/LTC2385 18-/16-Bit, 15Msps/10Msps/5Msps, High Speed SAR ADCs Description Demonstration circuit 2588A features the LTC 2387 family bits. The DC2588A demonstrates the AC performance of driven by a pair of ADA4899-1 driver amplifiers. With up the LTC2387 in conjunction with the DC718 data collec- to 15Msps, these differential input, single channel, 18-/16- tion board. The amplifiers simplify the task of driving the Bit, serial, high speed successive approximation register LTC2387 with a signal source. (SAR) ADCs are available in a 32-Pin QFN package. The Design files for this circuit board are available at LTC2387 family has an internal 20ppm/C reference and DEMO MANUAL DC2588A Dc 718 Quick s p D Connect the +10V, +6V and 5V DC power supplies to jitter 10dBm sine wave or square wave to connector J4. See the turrets as shown in Figure 1. Note the onboard LDO Table 1 for maximum clock frequencies. Note that J4 has outputs are available on the 2.5V, +1.2V, +2.5V, +3V, a 50 termination resistor to ground. Run the PScope +7.5V, V and V turrets. Connect the DC2588A to software (Pscope.exe version K73 or later) supplied with DD DDL a DC718 USB High Speed Data Collection Board using DC718 or download it from www.linear.com/software. edge connector J1. Connect the DC718 to a host PC with Complete software documentation is available from the a standard USB A/B cable. Apply a low noise differential Help menu. Updates can be downloaded from the Tools + signal to J6 (A ) and J5 (A ). Note that the DC2588A menu. Check for updates periodically as new features IN IN requires a differential input signal of approximately 8.192V may be added. The PScope software should recognize peak-to-peak to reach 0dBFS. If a differential signal source the DC2588A and configure itself automatically. Click of this amplitude is not available use one of the recom- the Collect button (Figure 2) to begin acquiring data. The mended differential amplifier demo boards available to Collect button then changes to Pause, which can be used increase the signal level. For a clock source, apply a low to stop data acquisition. Table 1. DC2588A Assembly Options VERSION U1 PART NUMBER MAX CONVERSION RATE OF BITS MAX CLOCK FREQUENCY DC2588A-A LTC2387CUH-18 PBF 15Msps 18 15MHz DC2588A-B LTC2387CUH-16 PBF 15Msps 16 15MHz DC2588A-C LTC2386CUH-18 PBF 10Msps 18 10MHz DC2588A-D LTC2386CUH-16 PBF 10Msps 16 10MHz DC2588A-E LTC2385CUH-18 PBF 5Msps 18 5MHz DC2588A-F LTC2385CUH-16 PBF 5Msps 16 5MHz h D s SIGNAL CONNECTIONS JUMPERS J2: JTAG. Factory use only. JP1: EEPROM. Factory use only. J3: FPGA Program. Factory use only. JP2: Lanes. Use this jumper to select either single lane or two lane data output mode from the LTC2387. The default J4: CLK IN. This input has a 50 termination resistor, setting is 1. The 1 setting clocks out all data on pin DA of and is intended to be driven by a low jitter, 10dBm sine the LTC2387. The 2 setting clocks out data alternately on or square wave. To achieve full AC performance of this pins DA and DB of the LTC2387. part, the clock jitter should be kept under 2ps . This RMS input is capacitively coupled so that the input clock can JP3: Test Pattern. Use this jumper to deliver a fixed repeat- be either 0V to 3.3V or 1.65V. This eliminates the need ing test pattern from the LTC2387. The default setting is for level shifting. To run at the maximum conversion rate, OFF. The output data will be 97796 if the jumper is in apply the frequency specified in Table 1. the ON position in 1 lane mode, and will be 52996 in 2 lane mode. J5: A Input. This is the negative signal input. IN JP4: ADC ON. Use this jumper to enable or disable the + J6: A Input. This is the positive signal input. IN ADC. The default setting is ON. dc2588af 2 etup ware ar ure roce tart