LTC6952 Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B/JESD204C Support FEATURES DESCRIPTION n JESD204B/C, Subclass 1 SYSREF Signal Generation The LTC 6952 is a high performance, ultralow jitter, n Low Noise Integer-N PLL JESD204B/C clock generation and distribution IC. It n Additive Output Jitter < 6fs includes a Phase Locked Loop (PLL) core, consisting of RMS (Integration BW = 12kHz to 20MHz, f = 4.5GHz) a reference divider, phase-frequency detector (PFD) with n Additive Output Jitter 65fs (ADC SNR Method) a phase-lock indicator, ultralow noise charge pump and RMS n EZSync, ParallelSync Multichip Synchronization integer feedback divider. The LTC6952s eleven outputs n 229dBc/Hz Normalized In-Band Phase Noise Floor can be configured as up to five JESD204B/C subclass n 281dBc/Hz Normalized In-Band 1/f Noise 1 device clock/SYSREF pairs plus one general purpose n Eleven Independent, Low Noise Outputs with output, or simply eleven general purpose clock outputs for Programmable Coarse Digital and Fine Analog Delays non-JESD204B/C applications. Each output has its own n Flexible Outputs Can Serve as Either a Device Clock individually programmable frequency divider and output or SYSREF Signal driver. All outputs can also be synchronized and set to n Reference Input Frequency up to 500MHz precise phase alignment using individual coarse half-cycle n LTC6952Wizard Software Design Tool Support digital delays and fine analog time delays. n 40C to 125C Operating Junction Temperature Range For applications requiring more than eleven total outputs, multiple LTC6952s can be connected together using the APPLICATIONS EZSync or ParallelSync synchronization protocols. n High Performance Data Converter Clocking All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 8319551 and 8819472. n Wireless Infrastructure n Test and Measurement TYPICAL APPLICATION 3.3V 3.3V + + + + LTC6952 Phase Noise V V V V VCO REF D OUT LTC6952Wizard REGISTER VALUES: 100 FILE: LTC6952 EZSync STANDALONE + 5V V RMS JITTER = 65fs CP OUT0 12.5MHz ADC SYSREF 48.7 EQUIVALENT ADC SNR METHOD OUT1 500MHz ADC CLOCK 110 CP NOTES 10, 13 22nF OUT2 12.5MHz ADC SYSREF 33nF 48.7 120 OUT3 500MHz ADC CLOCK OUT4 12.5MHz FPGA SYSREF 130 1.2F 0.47F OUT5 125MHz FPGA CLOCK LTC6952 140 OUT6 100MHz FPGA MGMT CLOCK 0.1F 30 Crystek + OUT7 12.5MHz DAC SYSREF 150 VCO CVCO55CC- OUT8 4GHz DAC CLOCK 4000-4000 0.1F 75 160 OUT9 12.5MHz DAC SYSREF 4GHz VCO OUT10 4GHz DAC CLOCK 500MHz Vtune 170 1k 10k 100k 1M 10M 40M 1F 1F 0.1F 100 OFFSET FREQUENCY (Hz) + + 6952 TA01b REF OUTx 49.9 100 Pascal OCXO-E REF 100MHz Ref Osc 1F OUTx + EZS SRQ 0.1F TO SYNC OUTPUTS: EZS SRQ OUTPUT TERMINATION DETAIL TOGGLE SSYNC REGISTER BIT 6952 TA01a Rev 0 1 Document Feedback For more information www.analog.com PHASE NOISE (dBc/Hz)LTC6952 TABLE OF CONTENTS Features ............................................................................................................................ 1 Applications ....................................................................................................................... 1 Typical Application ............................................................................................................... 1 Description......................................................................................................................... 1 Absolute Maximum Ratings ..................................................................................................... 4 Order Information ................................................................................................................. 4 Pin Configuration ................................................................................................................. 4 Electrical Characteristics ........................................................................................................ 5 Typical Performance Characteristics .......................................................................................... 9 Pin Functions .....................................................................................................................13 Block Diagram ....................................................................................................................15 Timing Diagrams ................................................................................................................16 Operation..........................................................................................................................17 Reference Input Buffer .......................................................................................................................................... 17 Reference Divider (R) ........................................................................................................................................... 18 Phase/Frequency Detector (PFD) .......................................................................................................................... 18 Lock Indicator ....................................................................................................................................................... 18 Charge Pump ........................................................................................................................................................ 19 Reference Aligned Output (RAO) Mode ................................................................................................................ 20 VCO Input Buffer ................................................................................................................................................... 20 VCO Divider (N) .................................................................................................................................................... 21 Output Dividers (M0 to M10) ................................................................................................................................ 21 Digital Output Delays (DDEL0 to DDEL10) ............................................................................................................ 21 Analog Output Delays (ADEL0 to ADEL10) ........................................................................................................... 21 CML Output Buffers (OUT0 to OUT10) ................................................................................................................. 22 Output Synchronization and SYSREF Generation .................................................................................................. 22 Serial Port ............................................................................................................................................................. 30 Block Power-Down Control ................................................................................................................................... 36 Applications Information .......................................................................................................37 Introduction .......................................................................................................................................................... 37 Output Frequency ................................................................................................................................................. 37 Loop Filter Design ................................................................................................................................................. 37 Digital and Analog Output Delays .......................................................................................................................... 38 Reference Input .................................................................................................................................................... 38 VCO Input ............................................................................................................................................................. 38 EZS SRQ Input ..................................................................................................................................................... 41 JESD204B/C Design Example Using EZSync Standalone ...................................................................................... 41 JESD204B/C Design Example Using Ezsync Multi-Chip ........................................................................................ 48 Reference Source Considerations ......................................................................................................................... 64 In-Band Output Phase Noise ................................................................................................................................. 65 Output Phase Noise Due To 1/f Noise ................................................................................................................... 65 Reference Signal Routing, Spurious, and Phase Noise ......................................................................................... 65 Supply Bypassing and PCB Layout Guidelines ...................................................................................................... 66 Rev 0 2 For more information www.analog.com