DEMO MANUAL DC273A LTC2408 4-/8-Channel 24-Bit Power No Latency ADC Description The LTC 2408, an 8-channel 24-bit no latency ADC is The board includes a precision 2.5V reference (LT1019- featured on the DC273A demonstration board. The LTC2408 2.5), as well as bypassing capacitors, and jumpers to select features a 4ppm linearity, 4ppm full-scale accuracy, 1ppm line frequency rejection and on board /external reference. offset accuracy, and 0.3ppm RMS noise. The demonstration board is designed to be incorporated The LTC2408 performs interleaved auto-zero and cali- into a target system, as well as give an example of good bration cycles which are transparent to the user. placement of bypass and partitioning of an analog and digital ground. The device does not require initialization or configuration, other than selecting the multiplexer channel. Design files for this circuit board are available at DEMO MANUAL DC273A Quick s p D All of the digital control lines are on a 0.070 header (J17). All ground connections should be as short as possible. On the DC273A demonstration board CSMUX and CSADC The multiplexer output is linked to the ADC through a 5k are tied together, as are SLK and CLK. This allows the ADC resistor. Both terminals are available, J11 for MUXOUT, to be addressed through a minimum of control lines. When and J12 for ADCIN. As the multiplexer output can be dis- the CSMUX and CSADC are logic High, address data can abled, multiplexer expansion can be brought to either of be clocked into the MUX. When CSMUX and CSADC are these terminals. Optionally, an amplifier (buffer) can be logic low, conversion data can be clocked out of the ADC. used to drive ADCIN, without necessarily removing the 5k Refer to the LTC2408 data sheet for a complete description resistor. If an amplifier with voltage gain is introduced, it of the various serial interface modes. is recommended that the resistor be removed. Depending on the source resistance or drive capabilities of nodes driv- The DC273A incorporates 2 jumpers: JP1, which allows ing the multiplexer inputs, J11 can be tied directly to J12. the on-board or an external reference, to be selected and Please see the LTC2400 data sheet for more information JP2, which allows selection of 50Hz/60Hz line frequency on driving the input of the LTC2408. rejection. See the timing diagram for MUX, and Data Output operation. All the analog inputs are provided with turrets along one edge of the board, positioned to be compatible with clip F0 is available on J17 for external conversion clock. See leads. Two ground connections (J9 and J10) are provided full data sheet for use of this line, otherwise, leave open. for interconnection into an analog subsystem or to be used Use of external clock requires removal of JP2. as separate returns for two signal groups. The LTC2408s F0 pin is available on J17 for those applica- Power and ground are provided on J15 and J16, and ref- tions where an external oscillator controls the conversion erence in and out are provided on J13 and J14. time of the ADC. JP2 must be removed in this case. Please consult the LTC2408 data sheet for more information on Interconnection of analog and digital subsystems can be the use of F0. If an external oscillator is not required, leave made through these ground connections, or all should pin 1 on J17 open. return to a star ground at a point in the target system. p List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER 1 2 C1, C2 CAP., TAN 10F 16V AVX, TAJB106M016, 3528 2 2 C3, C4 CAP., X7R 1F 10V AVX, 0805ZC105KAT1A, 0805 3 1 R2 RES., CHIP 3.3 5% TAD CR16-3R3JM, 0603 4 2 R3, R4 RES., CHIP 100 5% TAD CR16-101JM, 0603 5 1 R1 RES., CHIP 5.1k 5% TAD CR16-512JM, 0603 6 16 J1-J16 TERMINAL, TURRET .065 MIL-MAX 2308-02 7 2 JP1-JP2 HEADER, 31 .079 CENTER COMM CON 2802S-3G2 8 1 JP3 HEADER, 52 .079 CENTER COMM CON 2202S-10G2 9 3 JP1-JP3 SHUNT, CCIJ2MM-138-G COMM CON. CCIJ2MM-138-G 10 1 U2 IC., LT1019ACS8-2.5V LINEAR LT1019ACS8-2.5V, SO8 11 1 U1 IC., LTC2408CG LINEAR LTC2408CG dc273af 2 arts ure roce tart