QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 379 16-BIT, 250KSPS ADC LTC1606CG DESCRIPTION The LTC1606 is a 250Ksps ADC that draws only For best performance, the area immediately sur- 75mW from a Single +5V Supply. rounding the ADC should be used as a guideline for placement as well as interconnection of analog and Demonstration circuit 379 provides the user a means digital planes. of evaluating the performance of the device mounted on a PCB that is intended to demonstrate recom- Gerber files of this board are available online. Con- mended placement, routing and bypassing. sult factory or LTC sales for access. QUICK START PROCEDURE DC379 requires +5V at approximately 30mA and ADC if the clock high time is greater than 500nsec. A +/- 15V to power amplifier U4. 50% duty cycle clock at 250KHz is typically used to test these demo boards. Shorter duty cycle (active Even if you do not use buffer/amplifier U4 (see High at J1) can be used to a minimum of 40nsec. jumper JP4) you must provide +/-15V, as otherwise, the input circuitry in U4 will load your signal source Logic can be used to drive J1 if located close to the and cause distortion. board, in which case, the through terminator is not required. Note that slow CMOS buffers will translate The +5V supply powers the ADC directly without any supply fluctuations into variation in propagation de- protection for reverse bias, and no regulation. Poor lay, and will appear as clock jitter. regulation will compromise results reverse bias will damage the ADC. If you do not intend to use the Parallel data output from this board, if not used by a amplifier, you may remove it, in which case, only +5V target system, must be acquired by a logic analyzer, is required. and subsequently imported into a spreadsheet, or mathematical package depending on what form of J1 digital signal processing is desired. You must provide a low jitter logic level clock source JP5 allows output buffer/latch to be operated as a to J1. The rising edge of this signal defines the aper- transparent buffer, or as a latch. The choice is arbi- ture of the converter. Slow rising edges or un- trary, in many cases. However, JP5 can potentially be terminated cables may compromise SNR of the con- used to decimate the output, or for example latching verter in the presence of high-amplitude higher- only a given sample in a sequence to feed a DAC frequency input signals. This input is not terminated, Evaluations in some cases may be best performed by as a result, if you use a signal generator intended to feeding the output of the converter to a 16-bit DAC, drive 50-ohm loads, you must use a 50-ohm through- the output of which is used to subsequently drive a terminator at the input. Poor cables, clip leads, may spectrum analyzer, or a scope. The limitations of the or will compromise results. DAC must be recognized and accounted for in an The demo board incorporates an edge detector circuit evaluation of this type. If the signals of interest are in the form of an inverter (U6A) followed by a channels in a time domain multiplexed sequence, or a 500nsec delay, feeding, along with the original clock brief transient feature on a complex recurring wave- source, a two input NAND gate (U3). This will gener- form, the subsequent waveform at the output of a ate an approximate 500nsec active low pulse at the DAC latching only that channel may be much easier to 1 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 379 16-BIT, 250KSPS ADC interpret than the original signal. By placing a given to be evaluated, you will see better results with the frequency on the channel of interest, and a different amplifier in the signal path. frequency on another channel will allow you via the If you want to evaluate the amplifier in unity gain, re- DAC, feeding a spectrum analyzer to see cross talk move R10, or solder a low value resistor in parallel mechanisms in multiplexers. You can also use this with R9. If you want to evaluate the amplifier with technique to evaluate the effects of transient steps higher gain, you may reduce the value of R10. If you preceding the acquisition period. use very high quality resistors, you should be able to The demo board is typically shipped with Byte (JP2) increase the gain to 50 before the noise floor of the and CS (JP3) tied to ground. If you intend to operate converter rises discernibly. A voltage gain of 10 this device in a fashion that involves these lines, you should result in the typical SNR of 90dB dropping to can use the jumpers as a means of introducing these 89.9dB. A voltage gain of 50 should give approx signals from an external source. 88.7dB, and a gain of 100 would give approximately 86dB SNR. THD will increase but with a gain of 50, JP1 allows you to select between an on chip refer- the THD of the LT1468 is still typically in the range of ence (INT) or an external LT1019A-2.5. The typical -90dB. drift specifications of this reference are similar to the on chip reference, but The LT1019 has guaranteed If the amplifier is configured for high gain, ground maximums. potential differences between the various instruments on your bench top may be found to develop a differ- The demo board is shipped with JP4 in the out posi- ential component at the input to the demo board. tion, in which case, the input amplifier is not in the Transformer isolation may be required to produce signal path. With JP4 in the IN position, U4 good results with a gain of 50. The system used for (LT1468) provides a gain of 9dB, to allow a signal data collection may have a negative effect on how generator with 2.5V RMS output levels to drive the well the demo board performs, if it produces signifi- converter to full scale. This amplifier does not com- cant ground current through the demo board. promise the SNR or distortion performance of the converter. This demo board is tested in house by duplicating the FFT plot shown in the lower left of page 6 of the The input noise density of the LT1468 itself is LTC1606 data sheet. This involves using a low jitter, 5nV/ Hz. 250KHz clock source for the encode clock, (for ex- In the circuit as configured, the feedback network im- ample a 50MHz Oscillator divided by 200), along with pedance, and the amplifiers input noise current con- a low noise, low distortion sinusoidal generator at a tribute noise power to produce an input referred frequency in the neighborhood of 1KHz. noise density of 7.44nV// Hz With a gain of 2.82, this The FFT shown in the data sheet is a 4K point FFT, produces in the 675Khz bandwidth imposed by the with the input frequency at precisely 1037.5976Hz. converter, 17uV RMS, or a signal to noise ratio of This frequency is coherent (produces an integral 112dB at full scale. number of cycles of the fundamental within the win- This is of course not verifiable at the output of the dow) for a 250KHz clock frequency, and Prime (17 ADC. cycles). A prime number of integral cycles exercises the greatest number of possible input codes. Note With JP4 in the out position, the input impedance at that a 4K transform does not exercise all codes in a J2 is 10K-ohms. With JP4 in the IN position, the 16-bit converter. input impedance is very high. Other sample rates require different input frequen- If J2 is driven by a generator intended to drive a 50- cies. ohm impedance, you may want to use a 50-ohm through-terminator. If a higher impedance source is 2