DEMO MANUAL DC416 LTC1864 16-Bit 250ksps ADC Description Demonstration circuit 416 features the LTC1864 16-bit is hence much greater than what would be required in 250ksps analog-to-digital converter. almost any practical application. This board provides a means to evaluate the performance The LTC1864 and its demo board are intended to be used of the LTC1864 with either the Linear Technology PScope with the PScope data acquisition system for characteriza- data acquisition system, or with other parallel or serial tion of the ADC in AC applications extending from Hz to data acquisition systems. MHz. The full power bandwidth of the LTC1864 is high enough to produce good performance in under-sampling The board also demonstrates proper layout techniques in applications, as well as applications where the signal the circuitry surrounding the ADC and in the segmenta- content is below Nyquist. tion of the planes required to achieve full performance with the ADC. The board contains a bandwidth-limiting filter at the input of the ADC (C7, C8, C9, R1 and R2), as well as provision These techniques include proper grounding of the device for an amplifier (U2). This bandwidth-limiting filter (3dB at and associated bypass capacitors, placement of the device 1.5MHz) is typical of what may be required for many applica- relative to interconnection of analog and digital subsystems tions, but it is not necessarily the best for all applications. and signal routing in proximity to the ADC. The board also incorporates an LTC1799 resistor program- This board performs serial to parallel conversion in a man- mable oscillator as an optional clock source. ner that is unlikely to be used in an actual implementation, but is representative of what could be implemented in an Design files for this circuit board are available at FPGA. It is expected that with this ADC, the interface will DEMO MANUAL DC416 q s Dp 3. If the intent is to do an evaluation of AC performance, 5. Collect data via PScope for a Fourier transform into the connect a sinusoidal (or other) input signal to J1, or frequency domain, or to allow data to be collected and J1 and J2, with a nominal DC bias of 2.5V. If only J1 is saved to a file for subsequent import and analysis in used (single-ended operation), JP3 should be installed. Excel, Matlab or other analysis packages. This converter converts unipolar differential inputs from Duplication of the FFT results shown in the data sheet 0 V . REF requires the use of a low jitter clock and waveform genera- NOTE: The A inputs do not have 50 termination. Most tors synchronized such that the input waveform must be IN generators will produce the correct signal level only if the within a few ppm of an exact multiple of the conversion cable is terminated at 50. If you are driving this from clock divided by the FFT size (termed coherent). For 250kHz a generator, you should use 50 through terminators. sample rate and a 4096 point FFT, input frequencies should Take care not to overdrive the inputs if you do not use be an exact multiple of 61.035156Hz, and preferably a prime terminators. number multiple or at least an odd number multiple. The use of an even number multiple will exercise a minimal 4. Connect a 20MHz digital clock to CLKIN. With default number of codes, producing poor results. jumpers in place, this will result in a 250ksps conver- sion rate. IF U2 POPULATED WITH BIPOLAR AMPLIFIER + SIGNAL SOURCE PARALLEL DATA COLLECTION SYSTEM IF DIFFERENTIAL SIGNAL SOURCE CLOCK SOURCE USE EITHER SERIAL DATA PARALLEL OR SERIAL COLLECTION SYSTEM DATA COLLECTION SYSTEM DC416 F01 Figure 1. Proper Measurement Equipment Setup dc416f 2 + ure roce tart uick