QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 528 14-BIT / 6 MSPS ADC LTC1740 DESCRIPTION Demonstration circuit 528 is a quick way to try the Design files for this circuit board are available. LTC 1740, and gives a clean, compact example of a Call the LTC factory. PC board layout for the part. For a description of how LTC is a registered trademark of Linear Technology Corporation. the LTC1740 operates, please refer to the data sheet on the Linear Technology website. QUICK START PROCEDURE Connecting the Analog Power Supplies Driving the Analog Input The part can run off a single supply or dual supplies: Apply the analog input signal to the +AIN BNC connector. The negative analog input can be driven at the AIN BNC Single Supply: VDD=+5V, VSS=0V, AGND=0V connector. For convenience, the negative analog input can Dual Supplies: VDD=+5V, VSS= 5V, AGND=0V also be connected to VCM or AGND with JP2: JP2 on left two pins: -AIN=AGND Dual supply operation Connecting the Digital Output Power Supply JP2 on right two pins: -AIN=VCM (+2.5V) OVDD is the supply for the digital output drivers on the Single supply operation part. VCC is the supply for the 74ACT16373 transparent latch that buffers the outputs. For best results, set The analog input range, Vin = +AIN -AIN is: OVDD=VCC=+3V to +5V. Connect the ground of the -VREF/2 < Vin < +VREF/2 for PGA gain=1x digital output supply to OGND. Input RC filter SENSE pin jumpers For optimal AC performance, the LTC1740 should JP1 configures the SENSE pin, which sets the voltage have an NPO capacitor across its analog input (C6). reference, VREF. This capacitor can be used along with R18 as an input JP1 on right: SENSE=GND filter to reduce noise in the input signal. VREF=4.50V JP1 in middle: SENSE=VDD. VREF must be driven Driving the Clock Input externally. Input impedance is about 1k . Apply the encode clock to the CLK BNC connector. For best performance, the clock should have low jitter JP1 on left: SENSE=VREF and rise and fall times of less than 5ns. R17 is a 50 VREF=2.25V Ohm resistor that terminates the clock to ground. R17 should be removed if the clock signal source cannot drive a 50 Ohm load. 1 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 528 14-BIT / 6 MSPS ADC Digital Outputs be as short as possible. The output coding format is selected with JP3: The digital outputs appear at the 40-pin connector on the right side of the board. The signals are the JP3 on top two pins: 2s complement fourteen data bits, overflow, and a buffered version of JP3 on bottom two pins: straight binary the clock that can be used to latch the data. For best results all wires connected to the output bus should Figure 1. Proper Measurement Equipment Setup 2