QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 540 GENERAL PURPOSE DATA ACQUISITION BOARD LTC1604 and LTC1608 DESCRIPTION Demonstration circuit 540 is a general purpose Design files for this circuit board are avail- data acquisition board featuring the LTC1604 and able. Call the LTC factory. LTC1608 (version B) Analog to Digital converters. These two devices are pin compatible, and in terms of performance, almost indistinguishable up to 333 Ksps, the maximum conversion rate of the LTC1604. The LTC1608 has a maximum conver- sion rate of 500 Ksps, and may also offer per- formance advantages below 333 Ksps as the longer acquisition time relative to the LTC1604 may permit use of a slower settling drive amplifier. Both devices are 16 bit ADCs with +/- 2.5V fully differential inputs. Both exhibit 90 dB Sinad, and -100 dB spurious free dynamic range (with a 5kHz input signal). Table 1. Performance Summary (T = 25C) A PARAMETER CONDITION VALUE ADC Input Voltage Range 2.5V - + ADC Common Mode Input Voltage Range V < A , A <V SS IN IN DD SNR 100 kHz input (typical) 90 dB THD 100 kHz input (typical) -94 dB SFDR 100 kHz input (typical) 96 dB -3 dB bandwidth Source impedance <50 ohms 5 MHz Power consumption (LTC1604) V (5V) 30 mA max DD V (-5V) 40 mA max SS V (5V) 35 mA max DD Power consumption (LTC1608) V (-5V) 49 mA max SS OPERATING PRINCIPLES The LTC1604 and the LTC1608 are 16 Bit Suc- mounted device, an example of a well imple- cessive Approximation converters with no pipeline mented 4 layer PCB. The performance can be delay. Devices with this level of performance re- evaluated using a data collection tool such as a quire careful implementation of the PCB design in logic analyzer or Linear Technologys DATS data order to deliver full performance. This demo cir- collection system. As a reference design, it dem- cuit provides in addition to a functioning board onstrates proper placement of bypassing, signal 1QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 540 GENERAL PURPOSE DATA ACQUISITION BOARD routing, and interconnection of analog and digital Gain in dB is 20*log(1+(804/R15)) grounds at the converter. Other circuitry incorporated on the Demo Board Other placement schemes involving components allows experimentation with various low pass filter on the bottom side, and different geometries in the networks between the amplifier and the ADC. The various planes may also work, but must be im- circuitry as populated is a second order network, plemented with forethought about the effects of via with a first pole at 800 kHz, and a second pole at placement with respect to underlying planes, the 10 MHz. This second pole is intended primarily to effects of lead inductance, parasitic capacitance attenuate reverse transfer of high frequency sam- between planes, planes and pads etcetera. pling spikes that may result in envelope detection Transmission line effects and the associated mir- in the amplifier input stage, or may produce dis- rored current flow through underlying planes must turbances that do not settle out in the time avail- be well thought out. If time for a complete under- able to the amplifier. The worst case settling time standing of the effects of the various parasitics is is at the maximum conversion rate with a con- not available, the layout of the area surrounding verter that has the maximum permissible conver- the ADC on the demo board should be duplicated sion time. to the letter. A two layer board is generally not ad- This is 200 ns with the LT1608* at 500 Ksps, al- visable. If you intend to put a two layer design into though typically the amplifier will have 550 nsec to production, use the back side as a complete unin- settle. terrupted ground plane, or contact the factory for *Also, 200 ns worst case for the LT1604 at 333 assistance. If you intend to implement a board Ksps. with 6, 8 or more layers, the 4 layer design can be used as a model, but do not use those other lay- The LTC1608 at 333 Ksps would only require that ers for power planes. There is typically about 150 the amplifier settle in 1.2 s. pF/sq inch between layers in multilayer PCBs. (6 The settling time published for the LT1469 is 900 mil K=4) Most difficulties in getting a high per- ns, but this is for a large step. In response to a formance ADC to perform to spec are related to small disturbance, it may settle within 200 ns. layout. See the Layout Tips section at the end of this document for additional layout guidance. The pole at 800 kHz is intended to limit the input noise bandwidth. Although the amplifier may be The DC540 demo board requires in addition to rolled-off at a lower frequency, the unity gain the analog inputs, and power (+/-5V), an external bandwidth of the amplifier extends to 40-50 MHz, TTL or CMOS logic level clock at the desired con- and peaks over a broad range in the neighbor- version rate. The output data lines are buffered to hood of 20 MHz. While the full power (-3dB) band- permit driving a short cable. A long flat cable may width of the converter is typically 5 MHz, thereafter result in degraded SNR. The board also incorpo- the converter input has a first order roll-off. The rates an optional input buffer/amplifier using the effective noise bandwidth may be as high as 20 LT1469. This should be placed in the signal path if MHz considering the peaking. If this full noise a high impedance source is used, or if gain is re- bandwidth from the LT1469 were present at the quired. Consult the included schematic and layout ADC input, the SNR would be reduced slightly. if you intend to modify the function of this ampli- The input network may be modified if desired to fier. As populated this amplifier provides 19.1 dB produce a true second order response, or with of differential gain. These amplifiers are unity gain components removed to evaluate the performance stable, and can be configured for unity gain by with fewer components. This network is not in- removing R15, or for other gains by changing R15 tended as an anti-aliasing filter. (100 to other values. 2