DEMO MANUAL DC547A LTC1864L 16-Bit, 150ksps, 3V ADC Description Demonstration circuit 547A features the LTC1864L 16-bit is hence much greater than what would be required in 150ksps analog-to-digital converter. almost any practical application. This board provides a means to evaluate the performance of The LTC1864L and its demo board are intended to be the LTC1864L with either the Linear Technology PScope used with the PScope data acquisition system for char- data acquisition system, or with other parallel or serial acterization of the ADC in AC applications extending from data acquisition systems. DC to 1.5MHz. The full power bandwidth of the LTC1864L is high enough to produce good performance in under- The board also demonstrates proper layout techniques in sampling applications, as well as applications where the the circuitry surrounding the ADC and in the segmenta- signal content is below Nyquist. tion of the planes required to achieve full performance with the ADC. The board contains a bandwidth-limiting filter at the input of the ADC (C7, C8, C9, R1 and R2), as well as provision These techniques include proper grounding of the device for an amplifier (U2). This bandwidth-limiting filter (3dB and associated bypass capacitors, placement of the device at 1.5MHz) is typical of what may be required for many relative to interconnection of analog and digital subsystems applications, but it is not necessarily the best for all ap- and signal routing in proximity to the ADC. plications. This board performs serial to parallel conversion in a man- The board also incorporates an LTC1799 resistor pro- ner that is unlikely to be used in an actual implementation, grammable oscillator as an optional clock source. but is representative of what could be implemented in an FPGA. It is expected that with this ADC, the interface will Design files for this circuit board are available at be performed serially with either programmable logic, a DEMO MANUAL DC547A q s Dp NOTE: The A inputs do not have 50 termination. Most Duplication of the FFT results shown in the data sheet IN generators will produce the correct signal level only if the requires the use of a low jitter clock and waveform gen- cable is terminated at 50. If you are driving this from erators synchronized such that the input waveform must a generator, you should use 50 through terminators. be within a few ppm of an exact multiple of the conver- Take care not to overdrive the inputs if you do not use sion clock divided by the FFT size (termed coherent). For terminators. 125kHz sample rate and a 4096 point FFT, input frequen- cies should be an exact multiple of 30.51757813Hz, and 3. Connect an 8MHz digital clock to CLKIN. With default preferably a prime number multiple or at least an odd jumpers in place, this will result in a 125ksps conver- number multiple. The use of an even number multiple sion rate. will exercise a minimal number of codes, producing 4. Collect data via PScope for a Fourier Transform into poor results. the frequency domain, or to allow data to be collected and saved to a file for subsequent import and analysis in Excel, Matlab or other analysis packages. IF U2 POPULATED WITH BIPOLAR AMPLIFIER + SIGNAL SOURCE PARALLEL DATA COLLECTION SYSTEM IF DIFFERENTIAL SIGNAL SOURCE CLOCK SOURCE USE EITHER SERIAL DATA PARALLEL OR SERIAL COLLECTION SYSTEM DATA COLLECTION SYSTEM DC547 F01 Figure 1. Proper Measurement Equipment Setup dc547af 2 + ure roce tart uick