QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 552 12-BIT 10MSPS ADC LTC1420CGN DESCRIPTION Demonstration circuit 552 is a quick way to try the Design files for this circuit board are available. Call LTC1420, and gives a clean, compact example of a PC the LTC factory. board layout for the part. For a description of how the LTC is a trademark of Linear Technology Corporation LTC1420 operates, please refer to the data sheet on the Linear Technology web-site. QUICK START PROCEDURE CONNECTING THE ANALOG POWER SUPPLIES GAIN PIN JUMPER The part can run off of a single supply or dual sup- JP4 configures the GAIN pin, which sets the gain of plies: the input PGA. Single Supply: VDD=+5V, VSS=0V, GND=0V No jumper: GAIN pin is connected to the GAIN post. Drive externally with CMOS logic Dual Supplies: VDD=+5V, VSS=-5V, GND=0V levels. Left 2 pins: GAIN=GND PGA gain = 2x CONNECTING THE DIGITAL OUTPUT POWER Right 2 pins: GAIN=VDD PGA gain = 1x SUPPLY OVDD is the supply for the digital output drivers on the part. VCC is the supply for the 74ACT16373 DRIVING THE ANALOG INPUT transparent latch that buffers the outputs. For best Apply the analog input signal to the +AIN BNC con- results, set OVDD=VCC=+3V to +5V. Connect the nector. The negative analog input can be driven at the ground of the digital output supply to GND. AIN BNC connector. For convenience, the negative analog input can also be connected to VCM or GND with JP5: SENSE PIN JUMPERS JP5 on left two pins: -AIN=GND JP1, JP2 and JP3 configure the SENSE pin, which Dual supply operation sets the voltage reference, VREF. JP5 on right two pins: -AIN=VCM (+2.5V) JP1: SENSE=GND VREF=4.096V Single supply operation JP2: SENSE=VDD VREF must be driven externally. Input The analog input range, Vin = +AIN - -AIN is: impedance is about 1kW. -VREF/2 < VIN < +VREF/2 for PGA gain=1x JP3: SENSE=VREF VREF=2.048V -VREF/4 < VIN < +VREF/4 for PGA gain=2x 1 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 552 12-BIT 10MSPS ADC INPUT RC FILTER DIGITAL OUTPUTS For optimal AC performance, the LTC1420 should The digital outputs appear at the 40-pin connector on have an NPO capacitor across its analog input (C6). the right side of the board. The signals are the twelve This capacitor can be used along with R18 as an in- data bits, overflow, and a buffered version of the put filter to reduce noise in the input signal. clock that can be used to latch the data. For best re- sults all wires connected to the output bus should be as short as possible. The output-coding format is se- DRIVING THE CLOCK INPUT lected with JP6: Apply the encode clock to the CLK BNC connector. JP6 on top two pins: 2s complement For best performance, the clock should have low jitter JP6 on bottom two pins: straight binary and rise and fall times of less than 5ns. R17 is a 50 Ohm resistor that terminates the clock to ground. R17 should be removed if the clock signal source cannot drive a 50 Ohm load. Figure 1. Proper Measurement Equipment Setup 2